Apparatus and method for CDMA Time Pseudolite for repeater identification

    公开(公告)号:AU2005291961A1

    公开(公告)日:2006-04-13

    申请号:AU2005291961

    申请日:2005-09-28

    Applicant: QUALCOMM INC

    Abstract: Apparatus and method for resolving repeater location ambiguities in a CDMA network using a CDMA Time Pseudolite. The CDMA Time Pseudolite includes a CDMA receiver to receive a CDMA signal with an embedded CDMA timing, a baseband processor to extract the CDMA timing and to adjust the CDMA timing to derive a signal with GNSS-like timing; and a GNSS transmitter to generate a GNSS-like signal and to transmit the GNSS-like signal to a mobile station. In one embodiment, the CDMA Time Pseudolite is situated at or nearby a CDMA signal repeater so that a mobile station may unambiguously identify a received CDMA signal as being transmitted by a particular CDMA signal repeater and then using that received CDMA signal for position determination of the mobile station.

    METHOD AND APPARATUS FOR WIRELESS NETWORK HYBRID POSITIONING

    公开(公告)号:CA2530892A1

    公开(公告)日:2005-01-13

    申请号:CA2530892

    申请日:2004-06-28

    Applicant: QUALCOMM INC

    Abstract: Methods and apparatuses for position determination and other operations. In one embodiment of the present invention, a mobile station uses wireless signals from a plurality of wireless networks (e.g., with different air interfaces and/or operated by different service providers) for position determination (e.g., for data communication, for obtaining time and/or frequency information, for range measurement, for sector or altitude estimation). In one embodiment of the present invention, mobile stations are used to harvest statistical data about wireless access points (e.g., the locations of mobile stations that have received signals from the wireless access points, such as from cellular base stations, wireless local area network access points, repeaters for positioning signals, or other wireless communication transmitters) and to derive location information (e.g., positi on and coverage area of the wireless access points) for the wireless networks from the collected statistical data.

    DISTRIBUIDOR DE TURBO CODIGO QUE UTILIZA SECUENCIAS CONGRUENTES LINEALES.

    公开(公告)号:MXPA01005573A

    公开(公告)日:2002-06-04

    申请号:MXPA01005573

    申请日:1999-12-03

    Applicant: QUALCOMM INC

    Abstract: Un distribuidor de turbo codigo (100) que utiliza secuencias congruentes lineales puede emplearse como un distribuidor de dos dimensiones (16) en un turbo codificador (10) que incluye tambien los codificadores constituyentes primero y segundo (12, 14). El distribuidor (16) y el primer codificador (12) se configuran cada uno para recibir los bits de entrada. El primer codificador (12) produce los simbolos de salida (22,24) a partir de los mismos. El distribuidor (16) recibe los bits de entrada (20) secuencialmente por hilera. Un algoritmo de repeticion de secuencia congruente lineal dentro del distribuidor (16) sirve para volver a colocar seudoaleatoriamente, o distribuir, los bits dentro de cada hilera del distribuidor (16). Los bits (26) se entregan como salida por el distribuidor secuencialmente por columna . El segundo codificador (14 ) se configura para recibir los bits distribuidos provenientes del distribuidor. El segundo codificador (14) produce simbolos de salida (28) a partir de ellos. Los dos flujos de simbolos de salida (22, 24 ) se multiplexan conjuntamente, con una perforacion apropiada. Si se desea, la secuencia de repeticion congruente lineal puede generarse en inverso. Si se desea tambien, puede utilizarse una tecnica de inversion de bit en el distribuidor (16) para volver a colocar, o distribuir , las hileras del distribuidor (16).

    67.
    发明专利
    未知

    公开(公告)号:NO20012708L

    公开(公告)日:2001-07-20

    申请号:NO20012708

    申请日:2001-06-01

    Applicant: QUALCOMM INC

    Abstract: A turbo code interleaver (100) using linear congruential sequences may be employed as a two-dimensional interleaver (16) in a turbo coder (10) that also includes first and second constituent encoders (12, 14). The interleaver (16) and the first encoder (12) are each configured to receive input bits. The first encoder (12) produces output symbols (22, 24) therefrom. The interleaver (16) receives the input bits (20) sequentially by row. A linear congruential sequence recursion algorithm within the interleaver (16) serves to pseudo-randomly rearrange, or shuffle, the bits within each row of the interleaver (16). The bits (26) are then output from the interleaver sequentially by column. The second encoder (14) is configured to receive the interleaved bits from the interleaver. The second encoder (14) produces output symbols (28) therefrom.; The two streams of output symbols (22, 24) are multiplexed together, with appropriate puncturing. If desired, the linear congruential recursion sequence can be generated in reverse. Also if desired, a bit reversal technique can be used in the interleaver (16) to rearrange, or shuffle, the rows of the interleaver (16).

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