公开(公告)号：WO2013109651A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021777

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter, G. ,  MAMIDI, Suman ,  ABRAHAM, Elizabeth ,  VENKUMAHANTI, Suresh, K. ,  CODRESCU, Lucian

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/381 ,  G06F9/383

Abstract: Systems and methods for prefetching cache lines into a cache coupled to a processor. A hardware prefetcher is configured to recognize a memory access instruction as an autoincrement-address (AIA) memory access instruction, infer a stride value from an increment field of the AIA instruction, and prefetch lines into the cache based on the stride value. Additionally or alternatively, the hardware prefetcher is configured to recognize that prefetched cache lines are part of a hardware loop, determine a maximum loop count of the hardware loop, and a remaining loop count as a difference between the maximum loop count and a number of loop iterations that have been completed, select a number of cache lines to prefetch, and truncate an actual number of cache lines to prefetch to be less than or equal to the remaining loop count, when the remaining loop count is less than the selected number of cache lines.

Abstract translation: 将高速缓存线预取到耦合到处理器的高速缓存中的系统和方法。 硬件预取器被配置为将存储器访问指令识别为自动增量地址（AIA）存储器访问指令，从AIA指令的增量字段推断步幅值，并且基于步幅值将预取行预取到高速缓存中。 另外或替代地，硬件预取器被配置为识别预取的高速缓存行是硬件循环的一部分，确定硬件循环的最大循环计数，以及剩余循环计数作为最大循环计数和循环数之间的差 已经完成的迭代，当剩余循环数小于选定数量的缓存时，选择要预取的高速缓存行数，并将实际数量的缓存行预截取为小于或等于剩余循环计数 线。

公开(公告)号：WO2012151334A1

公开(公告)日：2012-11-08

申请号：PCT/US2012/036199

申请日：2012-05-02

Applicant: QUALCOMM INCORPORATED ,  LARIN, Sergei ,  CODRESCU, Lucian ,  DAS GUPTA, Anshuman

Inventor： LARIN, Sergei ,  CODRESCU, Lucian ,  DAS GUPTA, Anshuman

IPC: G06F9/30

CPC classification number: G06F9/30178 ,  G06F9/30149 ,  G06F2211/1014 ,  G06F2212/401

Abstract: A custom entropy bounded encoding in an X-index and Y-index format is generated for a segment of program code, along with a custom decoding dictionary made up of an X pattern memory and a Y pattern memory. In run time decoding, a mix mask is used with an X pattern selected from the X pattern memory according to the X-index and with a Y pattern selected from the Y pattern memory according to the Y-index to determine an executable instruction. The mix mask identifying the order of bits to combine from the X pattern and the Y pattern. Appropriate hardware implementation and placement of the decoding mechanism and address translation is described during execution of an encoded code segment. Methods, including a genetic process, are also described to determine the X-index, the Y-index, the X patterns, the Y patterns, and one or more mix masks.

Abstract translation: 针对程序代码段生成X索引和Y索引格式的自定义熵有界编码，以及由X模式存储器和Y模式存储器组成的自定义解码字典。 在运行时解码中，使用根据X索引从X图案存储器中选择的X图案和根据Y索引从Y图案存储器中选择的Y图案来确定可执行指令的混合掩码。 混合掩模识别从X图案和Y图案组合的位的顺序。 在编码代码段的执行期间描述适当的硬件实现和解码机制的布局和地址转换。 还描述了包括遗传过程的方法以确定X指数，Y指数，X图案，Y图案和一个或多个混合掩模。

公开(公告)号：WO2011149828A1

公开(公告)日：2011-12-01

申请号：PCT/US2011/037537

申请日：2011-05-23

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich J. ,  VENKUMAHANTI, Suresh K.

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich J. ,  VENKUMAHANTI, Suresh K.

IPC: G06F9/455 ,  G06F9/30

CPC classification number: G06F9/322 ,  G06F9/26 ,  G06F9/328

Abstract: A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter. The apparatus also includes a decode unit configured to receive the second instruction from the location and to decode the second instruction to generate a decoded second instruction without changing the program counter to point to the second instruction. The first and second instruction are virtual machine instructions and the execute unit is adapted to interprete these virtual machine instructions.

Abstract translation: 公开了一种用于评估数据值作为指令的系统和方法。 例如，被配置为执行程序代码的装置包括执行单元，被配置为执行与第二指令的位置相关联的第一指令。 第一条指令由程序计数器识别。 所述装置还包括：解码单元，被配置为从所述位置接收所述第二指令，并且解码所述第二指令以生成解码的第二指令，而不改变所述程序计数器以指向所述第二指令。 第一和第二指令是虚拟机指令，并且执行单元适于分配这些虚拟机指令。

公开(公告)号：WO2011109476A1

公开(公告)日：2011-09-09

申请号：PCT/US2011/026815

申请日：2011-03-02

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant ,  VENKUMAHANTI, Suresh K. ,  TABONY, Charles Joseph

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/30149

Abstract: A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

Abstract translation: 公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。 在特定实施例中，公开了一种处理指令的方法。 该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。 响应于确定指令包括子分组，该方法还包括执行每个子指令。

公开(公告)号：WO2009158370A2

公开(公告)日：2009-12-30

申请号：PCT/US2009/048370

申请日：2009-06-24

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  WANG, Lin ,  VENKUMAHANTI, Suresh, K.

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  WANG, Lin ,  VENKUMAHANTI, Suresh, K.

IPC: G06F9/445

CPC classification number: G06F8/4452 ,  G06F9/30072 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

Abstract: Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.

Abstract translation: 公开了回路控制系统和方法。 在特定实施例中，硬件回路控制逻辑电路包括检测单元以检测程序循环的循环指示符的结束。 硬件回路控制逻辑电路还包括递减单元，用于递减循环计数并递减谓词触发计数器。 硬件循环控制逻辑电路还包括比较单元，用于将谓词触发计数器与参考值进行比较，以确定何时设置谓词值。

公开(公告)号：WO2009142928A1

公开(公告)日：2009-11-26

申请号：PCT/US2009/043331

申请日：2009-05-08

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian

Inventor： CODRESCU, Lucian

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30189 ,  G06F9/3806 ,  G06F9/3844

Abstract: A multi-mode register file for each thread of a multi-thread system is described. In one embodiment, the multi-mode register file includes an operand for the thread in a first mode. The multi-mode register file further includes branch prediction information which replaces the operand in a second mode.

Abstract translation: 描述了多线程系统的每个线程的多模式寄存器文件。 在一个实施例中，多模式寄存器文件包括在第一模式中线程的操作数。 多模式寄存器文件还包括在第二模式中替换操作数的分支预测信息。

公开(公告)号：WO2009108463A1

公开(公告)日：2009-09-03

申请号：PCT/US2009/032920

申请日：2009-02-03

Applicant: QUALCOMM Incorporated ,  INGLE, Ajay A. ,  PLONDKE, Erich J. ,  CODRESCU, Lucian

Inventor： INGLE, Ajay A. ,  PLONDKE, Erich J. ,  CODRESCU, Lucian

IPC: G06F12/12

CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

Abstract: A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same.

Abstract translation: 描述用于确定要替换的高速缓存行的系统。 在一个实施例中，系统包括包括多个高速缓存行的高速缓存。 该系统还包括被配置为识别用于替换的高速缓存行的标识符。 该系统还包括被配置为确定从增量器，高速缓存维护指令中选择的标识符的值的控制逻辑，或保持相同。

公开(公告)号：WO2008061086A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084523

申请日：2007-11-13

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

CPC classification number: G06F1/3203 ,  G06F11/362 ,  G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。 在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。 控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。 控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。 在调试寄存器和核心处理器处理或调试过程之间传输数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

公开(公告)号：WO2008016856A1

公开(公告)日：2008-02-07

申请号：PCT/US2007/074639

申请日：2007-07-27

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  ZENG, Mao

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  ZENG, Mao

IPC: G06F9/302 ,  G06F9/308 ,  G06F9/312

CPC classification number: G06F9/30043 ,  G06F9/30014 ,  G06F9/30018

Abstract: A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a processing unit. The instruction includes a shifting bit value indicating the bit amount for a right shift operation and is subsequently executed to shift data within the source register unit to the right by an encoded bit value, calculated by subtracting a single bit from the shifting bit value contained within the instruction. A predetermined bit extension is further inserted within the vacated bit positions adjacent to the shifted data. Subsequently, an addition operation is performed on the shifted data and a unitary integer value is added to the shifted data to obtain resulting data. Finally, the resulting data is further shifted to the right by a single bit value and a predetermined bit extension is inserted within the vacated bit position to obtain the final rounded data results to be stored within a destination register unit.

Abstract translation: 描述了在执行单个指令期间在微处理器（例如数字信号处理器）内执行移位和舍入操作的方法和系统。 在处理单元内接收用于在寄存器堆结构的源寄存器单元内移位和舍入数据的指令。 该指令包括指示右移位操作的位量的移位位值，并且随后被执行以将源寄存器单元内的数据向右移位编码位值，该编码位值通过从包含在其中的移位位值中减去单个位而被计算 指示。 进一步将预定比特扩展插入与移位数据相邻的空闲比特位置。 随后，对移位的数据执行相加操作，并将一个整数值加到移位数据上，以获得结果数据。 最后，所得到的数据进一步向右移位一个位值，并且将预定的位扩展插入到空出的位位置中，以获得存储在目的地寄存器单元内的最终舍入数据结果。

公开(公告)号：WO2008008999A1

公开(公告)日：2008-01-17

申请号：PCT/US2007/073535

申请日：2007-07-13

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  JANJANAM, Vijaya Kumar

Inventor： CODRESCU, Lucian ,  PLONDKE, Erich ,  AHMED, Muhammad ,  JANJANAM, Vijaya Kumar

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/684

Abstract: A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.

Abstract translation: 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，获取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。