中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

72 records (took 0.032 seconds)

    METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION
    64.
    发明授权
    METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION 有权
    用于分频单元同步的方法和设备

    公开(公告)号：EP2283406B1

    公开(公告)日：2018-01-03

    申请号：EP09739686.5

    申请日：2009-04-29

    Applicant: Qualcomm Incorporated

    Inventor： SUN, Bo ,  ANIRUDDHAN, Sankaran ,  SRIDHARA, Sriramgopal

    IPC: G06F1/12 ,  G06F1/32

    CPC classification number: G06F1/12 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.

    LOW POWER AND DYNAMIC VOLTAGE DIVIDER AND MONITORING CIRCUIT
    65.
    发明公开
    LOW POWER AND DYNAMIC VOLTAGE DIVIDER AND MONITORING CIRCUIT 审中-公开
    动态低电源分割装置和监控

    公开(公告)号：EP2972423A1

    公开(公告)日：2016-01-20

    申请号：EP14714519.7

    申请日：2014-03-10

    Applicant: Qualcomm Incorporated

    Inventor： SUN, Bo

    IPC: G01R19/165 ,  G01R15/08 ,  G01R15/04 ,  G05F1/46 ,  G01R15/09

    CPC classification number: G05F3/08 ,  G01R15/04 ,  G01R15/08 ,  G01R15/09 ,  G01R19/16519 ,  G01R19/16552 ,  G05F1/465

    Abstract: A voltage divider circuit (103) is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches (102, 104, 106) having different divider factors to divide the supply voltage (VDD) and obtain a divided supply voltage (Vm_A, Vm_B, Vm_i). Additionally, a control circuit (112) is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select (116) a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range.

    SIGNAL DECIMATION TECHNIQUES BASED ON A CONFIGURABLE FREQUENCY DIVIDER AND A CONFIGURABLE DELAY
    68.
    发明公开
    SIGNAL DECIMATION TECHNIQUES BASED ON A CONFIGURABLE FREQUENCY DIVIDER AND A CONFIGURABLE DELAY 审中-公开
    SIGNALDEZIMIERUNGSVERFAHREN基于可配置的分频器的和可配置的继电器

    公开(公告)号：EP2522071A2

    公开(公告)日：2012-11-14

    申请号：EP10801309.5

    申请日：2010-12-15

    Applicant: Qualcomm Incorporated

    Inventor： BALLANTYNE, Gary John ,  GENG, Jifeng ,  SUN, Bo

    IPC: H03B19/00 ,  H03D7/16 ,  G06F1/08

    CPC classification number: H03B19/00 ,  H03D7/165 ,  H03L7/16

    Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

    METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION
    70.
    发明公开
    METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION 有权
    方法和装置的纯度同步的部件

    公开(公告)号：EP2283406A1

    公开(公告)日：2011-02-16

    申请号：EP09739686.5

    申请日：2009-04-29

    Applicant: Qualcomm Incorporated

    Inventor： SUN, Bo ,  ANIRUDDHAN, Sankaran ,  SRIDHARA, Sriramgopal

    IPC: G06F1/12 ,  G06F1/32

    CPC classification number: G06F1/12 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    Abstract: A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.

Patent Agency Ranking