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公开(公告)号：JPH10333762A
公开(公告)日：1998-12-18
申请号：JP14142797
申请日：1997-05-30
Applicant: SONY CORP
Inventor： SONEDA MITSUO
Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption of the bias circuit of a current outputting device. SOLUTION: Currents running through a bias circuit constituted of MOS-FET 1, 4, and 5 are intermitted in a prescribed cycle by the MOS-FET 4. Switches 20 and 21 are turned into a connected state when the MOS-FET 4 is turned into a conducted state by a driving signal 2, and as a result, a prescribed charge is charged in an inter-gate and source capacity existing between each gate and source of the MOS-FET 1 and 5. When the charging of the charge is ended, the switches 20 and 21 are turned into an opened state, and the charge charged in the inter-gate and source capacity is held. Then, when the MOS-FET 4 is opened, currents Ix running through the bias circuit are turned into 0, and when the prescribed voltage by the charged charge is held between each gate and source of the MOS-FET 1 and 5, the similar voltage is impressed to the gates and sources of MOS-FET 2, 3, 6, and 7 at an output stage, and prescribed currents are outputted from output terminals 8, 9, 10, and 11.
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公开(公告)号：JPH0947018A
公开(公告)日：1997-02-14
申请号：JP18897095
申请日：1995-07-25
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: H02M3/07
Abstract: PROBLEM TO BE SOLVED: To realize a DC-DC converter producing a stabilized output voltage with low power loss. SOLUTION: Three capacitors 21, 22, 23 are connected in series between an external power supply and a reference power supply (ground) and charged based on clock signals ϕCK1 , ϕCK2 or they are connected in parallel to produce an output voltage Va having a level equal to the difference between the external power supply voltage and the reference power supply voltage. In such a QC-DC converter, a comparator 31 detects the external power supply voltage VCC, compares the vCC with a reference voltage Vref and delivers an output signal S31 to a switch circuit 13. The number of capacitors to be connected in series between the external power supply and the ground is switched depending on the level of the signal S31 .
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公开(公告)号：JPH08250607A
公开(公告)日：1996-09-27
申请号：JP4687995
申请日：1995-03-07
Applicant: SONY CORP
Inventor： TAKEDA MINORU , KUBOTA SHIGEO , SONEDA MITSUO , YAMAGISHI MACHIO
IPC: G03F7/20 , G11C16/02 , G11C17/00 , H01L21/82 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
Abstract: PURPOSE: To surely protect a semiconductor ROM device from illegal acts, such as theft, piracy acts, and illegal copy of software programs. CONSTITUTION: A semiconductor ROM device of MONOS structure includes a memory block where a pattern for certification data is written. The pattern is written as follows: The semiconductor ROM device is locally spot-irradiated with ultraviolet laser light. Part of the ultraviolet rays enters the interface between a gate oxide film 14 and a nitride film 14, under a gate electrode 11, which excites holes h. The excited holes h get over a potential barrier, present between the gate oxide film 14 and the nitride film 13, and is emitted on the Si substrate 15 side. Thus a memory block is provided in which the pattern of validation data is written.
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公开(公告)号：JP2530303B2
公开(公告)日：1996-09-04
申请号：JP22158184
申请日：1984-10-22
Applicant: SONY CORP
Inventor： SONEDA MITSUO , HAYASHI JUJI
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公开(公告)号：JPH08129891A
公开(公告)日：1996-05-21
申请号：JP26589094
申请日：1994-10-28
Applicant: SONY CORP
Inventor： SONEDA MITSUO , HASHIGUCHI AKIHIKO
IPC: G11C11/41 , G11C8/16 , G11C11/405
Abstract: PURPOSE: To shorten a readout time and to prevent power consumtion from increasing by setting and forming the threshold value voltage of the driving MOS transistor of a readout system lower than the threshold value voltage of an accessing MOS transistor. CONSTITUTION: A read-only circuit 2a is formed by connecting an accessing enhancement type NMOS transistor 22 whose threshold value voltage is set to a standard threshold value voltage to a driving enhancement type NMOS transistor 21a whose threshold value voltage is set lower than that of a standard enhancement type NMOS transistor and then by connecting the gate of the driving transistor 21a to the output node ND1 of an SRAM cell 1 and by connecting the gate of the accessing transistor 22 to a readout word line R-WL. Thus. the driving ability of the driving transistor 21a is improved and the operating speed of the transistor is made high speed, and the readout time is shortened.
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Patent Agency Ranking
公开(公告)号：JPH0818340A
公开(公告)日：1996-01-19
申请号：JP15005594
申请日：1994-06-30
Applicant: SONY CORP
Inventor： SEKI TAKEHIRO , SONEDA MITSUO
Abstract: PURPOSE:To prevent the influence of noise from the outside, to reduce the through current, and to reduce the power consumption. CONSTITUTION:A first current mirror circuit 3 is provided on the side of connection to a supply voltage VCC of a CMOS inverter 1 for voltage amplifier to which a quartz oscillator X1 is connected in parallel, and a second current mirror circuit 4 is provided on the side of connection to the earth as a second supply potential of this CMOS inverter 1. Currents flowing to a PMOS transistor TR 31 and an NMOS TR 41 are transferred to a PMOS TR 32 and an NMOS TR 42 respectively when a node n2 as the output end of the CMOS inverter 1 is charged/discharged to the supply voltage VCC and the earth level. A node n5 connected to the input of an inverter 2 for output is charged/discharged by the PMOS TR 32 and the NMOS TR 42 to which they are transferred.
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公开(公告)号：JPH0818339A
公开(公告)日：1996-01-19
申请号：JP15005494
申请日：1994-06-30
Applicant: SONY CORP
Inventor： SEKI TAKEHIRO , SONEDA MITSUO
Abstract: PURPOSE:To realize a quartz oscillation circuit capable of reducing the through current of an inverter circuit for oscillation and reducing the power consumption. CONSTITUTION:Boosting circuits 5 and 6 are provided which supply a voltage DVCC, which is obtained by reducing a supply voltage VCC by a prescribed voltage (a threshold voltage Vth), to a CMOS inverter 1 for voltage amplifier, to which a quartz oscillator X1 is connected in parallel, and a CMOS inverter 2 for waveform shaping connected to the output stage of this inverter 1 and consists of diode-connected MOS transistors. A level shifter 3 is provided which converts the logical level of the oscillation pulse of DVCC(=VCC-Vth) having the amplitude based on the reduced voltage to the VCC level. Thus, the through current of inverters 1 and 2 is reduced to reduce the power consumption.
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公开(公告)号：JPH07106946A
公开(公告)日：1995-04-21
申请号：JP24295593
申请日：1993-09-29
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: H03K5/02 , H03K3/012 , H03K3/356 , H03K17/16 , H03K19/0185
Abstract: PURPOSE:To eliminate the through current in a level shift mode and to reduce the power consumption for a level shifter by connecting a transistor TR to the 1st and 2nd TRs constructing a latch circuit for an input binary signal in order to prevent the current flow in a signal change mode. CONSTITUTION:The TR P1, P1', N1 and N1' construct a latch circuit which latches the input signal level. The TR P2 and P2' are connected to the TR P1 and P1' respectively to prevent the flow of a large through current that is caused in a level shift mode. Therefore a large current never flows even when the input logical level changes and the ON/OFF states of the TR P1 and P1' change. Thus the power consumption of a circuit is reduced. Furthermore the TR P3 and P3' are connected in parallel to the series connection of TR P1 and P2 and the series connection of TR P1' and P2' respectively. Thus the TR P3 and P3' are turned on in a level change mode. As a result, the potentials can be changed in a short time at the connection points (a) and (b).
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公开(公告)号：JPH06290595A
公开(公告)日：1994-10-18
申请号：JP10054493
申请日：1993-04-02
Applicant: SONY CORP
Inventor： SONEDA MITSUO
IPC: G11C17/00 , G11C16/06 , H03K17/16 , H03K19/0185
Abstract: PURPOSE:To obtain logical level conversion circuit for a non-volatile memory capable of realizing a device in which a through current of a VPP system power supply is prevented and power consumption is reduced and which has a single power source of lower voltage. CONSTITUTION:A PMOS transistor M1 and a NMOS transistor M2 are connected in series between a VPP system power source and ground, a capacitor C for clamp is connected between gates of these transistors M1 and M2. And a PMOS transistor M3 which controls charging to the capacitor C and a PMOS transistor M4 which controls a current flowing into this transistor M3 are connected in series between a node 1 and the VPP system power source, and a logic signal D1 (n) of a logical level of the VCC system is applied to a node 2. While, a logical signal D0 (n) of a logical level of the VPP system of which a level is converted form a node 3 is introduced.
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公开(公告)号：JPH0612638B2
公开(公告)日：1994-02-16
申请号：JP1975584
申请日：1984-02-06
Applicant: SONY CORP
Inventor： SONEDA MITSUO , HAZAMA YOSHIKAZU
IPC: H03K17/687 , G11C27/02
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