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公开(公告)号：US10451703B2
公开(公告)日：2019-10-22
申请号：US16213534
申请日：2018-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Condorelli , Daniele Mangano
Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.
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公开(公告)号：US10162038B2
公开(公告)日：2018-12-25
申请号：US14739195
申请日：2015-06-15
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Riccardo Condorelli , Daniele Mangano
Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.
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公开(公告)号：US10120006B2
公开(公告)日：2018-11-06
申请号：US15070509
申请日：2016-03-15
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Riccardo Condorelli , Daniele Mangano
Abstract: In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.
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公开(公告)号：US10019399B2
公开(公告)日：2018-07-10
申请号：US14940026
申请日：2015-11-12
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F17/50 , G06F13/36 , H04L12/933 , G06F15/78 , H04L12/935 , G06F13/40
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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公开(公告)号：US20170270070A1
公开(公告)日：2017-09-21
申请号：US15608857
申请日：2017-05-30
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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Patent Agency Ranking
公开(公告)号：US09697161B2
公开(公告)日：2017-07-04
申请号：US14219850
申请日：2014-03-19
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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公开(公告)号：US20170068594A1
公开(公告)日：2017-03-09
申请号：US15080307
申请日：2016-03-24
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Distefano , Antonin Fried
CPC classification number: G06F11/1068 , G06F11/1044 , G11C29/52
Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
Abstract translation: 一种方法包括：将第一数据存储在第一存储器模块的第一分区中，并将第二数据写入第二存储器模块的第一分区中，并且以第一操作模式和第二操作模式选择性地操作第一和第二存储器模块。 第一操作模式包括在第二存储器模块的第二分区中写入用于第一数据的奇偶校验位和在第一存储器模块的第二分区中写入用于第二数据的奇偶校验位。 第二操作模式包括在第一存储器模块和第二存储器模块中的一个或两个的第二分区中写入另外的数据而不是奇偶校验位。
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公开(公告)号：US20160070667A1
公开(公告)日：2016-03-10
申请号：US14940026
申请日：2015-11-12
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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公开(公告)号：US20150106778A1
公开(公告)日：2015-04-16
申请号：US14511014
申请日：2014-10-09
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F17/50
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
Abstract translation: 一种用于设计片上网络互连装置的系统包括具有多个骨干端口的片上网络骨干网以及提供各组片上系统功能的聚合IP功能集群的集合。 功能集群包括可连接到任何骨干端口的各个子网络，以及独立于片上网络骨干网骨源的源地图的功能集群中的任何其他功能集群。
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70.发明申请公开(公告)号：US20140344485A1
公开(公告)日：2014-11-20
申请号：US14278403
申请日：2014-05-15
Applicant: STMicroelectronics S.r.l.
Inventor： Mirko Dondini , Daniele Mangano , Giuseppe Falconeri
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.
Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。
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