公开(公告)号：FR2486339A1

公开(公告)日：1982-01-08

申请号：FR8112894

申请日：1981-06-30

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  OMURO SHIGERU ,  KITA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H03D1/22 ,  H04N5/455 ,  H04N5/48

Abstract: A synchronous detector for detecting an information signal modulated onto a carrier, such as a video IF signal, is disclosed in which there are provided a circuit for supplying the modulated information signal in the form of a vestigial sideband signal, a filter circuit coupled to the supplying circuit which includes a tuning circuit tuned to the frequency of the carrier on which the information signal is modulated, an emitter follower circuit connected to the output of the filter circuit, a limiter circuit connected to the filter circuit, for producing a switching carrier, and a multiplier having first and second input terminals coupled to the output of the limiter circuit and to the supplying circuit, for multiplying the modulated information signal and the switching carrier to obtain said information signal. In one embodiment, the limiter circuit includes a differential amplifier having first and second transistors, base electrodes of which are connected to the emitter follower circuit, and third and fourth common base transistors, emitter electrodes of which are respectively connected to collector electrodes of the first and second transistors and collector electrodes of which provide output terminals for supplying the switching carrier.

公开(公告)号：AU4562879A

公开(公告)日：1979-10-04

申请号：AU4562879

申请日：1979-03-30

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  OHMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H04N5/455 ,  H03D1/22 ,  H03D3/20 ,  H03D13/00 ,  H03J7/02 ,  H03J7/04 ,  H04N5/50 ,  H03J3/04 ,  H03J3/10

Abstract: In a system in which an intermediate frequency signal is synchronously detected using an intermediate frequency carrier signal derived from the intermediate frequency signal by means of a tuned circuit and a limiter circuit to remove amplitude variations therefrom, an automatic fine tuning signal is derived in a phase detector to which are fed the intermediate frequency carrier signal after its phase has been shifted 90 degrees in a phase shifter and either the intermediate frequency signal or the intermediate frequency carrier signal. When the intermediate frequency carrier signal is used in the phase detector, a second tuned circuit is used therein and buffering between the two tuned circuits prevents interaction therebetween.

公开(公告)号：AU3397278A

公开(公告)日：1979-09-13

申请号：AU3397278

申请日：1978-03-08

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KAWAKAMI HIROMI ,  YAMAMOTO YOSHIHIRO ,  TOKUHARA MASAHARU

IPC: H03B5/12 ,  H03B27/00 ,  H03D1/22

Abstract: An oscillating circuit provides first and second reference signals having a phase difference of 90 DEG with respect to each other. The oscillating circuit includes an oscillator providing the first reference signal at an output thereof, a voltage-to-current converting circuit, which may incorporate a common-base transistor, and a capacitor connected between the output of the oscillator and an input of the converting circuit. The output of the converting circuit then provides the second reference signal which differs in phase by 90 DEG from the first reference signal. The oscillator may include differentially connected transistors and an LC resonant circuit.

公开(公告)号：DE2814522A1

公开(公告)日：1978-10-12

申请号：DE2814522

申请日：1978-04-04

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  TOKUHARA MASAHARU ,  YAMAMOTO YOSHIHIRO ,  KAWAKAMI HIROMI

IPC: H04N5/455 ,  H03D1/00 ,  H03D1/04 ,  H03D1/22 ,  H04N5/44

Abstract: Demodulating apparatus for a modulated signal comprised of a carrier deriving circuit which is supplied with the modulated signal and which derives an unmodulated carrier therefrom, the carrier deriving circuit including a tuned circuit having a center frequency substantially coincident with the carrier frequency of the modulated signal and a limiter circuit in which the limiter circuit imparts a phase shift to the signal supplied thereto in connection with its elimination of the amplitude fluctuations in the signal produced by the tuned circuit. A synchronous detector receives the modulated signal and the derived carrier so as to detect the modulated signal with the derived carrier. A phase shift circuit supplies the synchronous detector with a phase shifted modulated signal, the phase shift substantially compensating for the phase shift imparted by the limited circuit in the carrier deriving circuit, whereby the modulated signal and the carrier which are applied to the synchronous detector are substantially in phase with each other.

公开(公告)号：DE2741697A1

公开(公告)日：1978-03-23

申请号：DE2741697

申请日：1977-09-16

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KAWAKAMI HIROMI ,  TOKUHARA MASAHARU

IPC: H04N5/455 ,  H03D1/22 ,  H03J7/02 ,  H03J7/04 ,  H04B1/26 ,  H04N5/50 ,  H03J3/10

Abstract: A television receiver has an automatic fine tuning circuit with a first phase-locked loop including a first low pass filter and a synchronous video detector with a second phase-locked loop including a second low pass filter. The cut off frequency of the first low pass filter is selected lower than the cut-off frequency of the second low pass filter, thereby enabling a stable operation of two phase-locked loops simultaneously.

公开(公告)号：DE69323947T2

公开(公告)日：1999-09-16

申请号：DE69323947

申请日：1993-09-16

Applicant: SONY CORP

Inventor： KITA HIROYUKI ,  SARUGAKU TOSHIO ,  TOKUHARA MASAHARU

IPC: H04N9/64 ,  H04N9/78

Abstract: In a luminance and chrominance signal separation circuit, when comparing circuits thereof decide that the level of high-frequency components of a luminance signal is lower than a predetermined level, a switching circuit, controlled by a control circuit, selects and outputs a chrominance signal output from a band pass filter processing circuit.

公开(公告)号：DE69225732T2

公开(公告)日：1998-09-24

申请号：DE69225732

申请日：1992-03-03

Applicant: SONY CORP

Inventor： SARUGAKU TOSHIO ,  KAWASHIMA HIROYUKI ,  KITA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N5/14 ,  H04N7/01 ,  H04N9/64 ,  H04N11/20 ,  H04N5/44

Abstract: Disclosed is a television receiver for extended definition television, the receiver carrying out scanning line interpolation in a way that eliminates picture shift on the screen and ensures normal display when supplied with a non-standard video signal having a scanning line count of other than 262.5 per field. The television receiver comprises scanning line interpolation means, normal video signal detection means and interpolation control means. The scanning line interpolation means effects scanning line interpolation using either data in the current field or out-of-field data as per the result of motion detection in the picture. The normal video signal detection means distinguishes the normal video signal from other signals by detecting the number of the scanning lines involved. The interpolation control means causes the scanning line interpolation means to effect scanning line interpolation using only the inside-field data if the supplied signal is a non-standard signal.

公开(公告)号：DE68927597T2

公开(公告)日：1997-06-26

申请号：DE68927597

申请日：1989-07-18

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  KAWASHIMA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N7/01 ,  H04N11/20 ,  H04N5/44

Abstract: Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit 501y,502y,503y; 501C,502C,503C, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal b in a given field, the next succeeding scan line signal c in that field, an interlaced scan line signal a in the next succeeding field and an interlaced scan line signal d in the next preceding field. A first combining circuit 504y,504C combines the signal values of the next succeeding field interlaced scan line signal a and the next preceding field interlaced scan line signal d to form a first combined scan line signal. A second combining circuit 505y;505C combines the signal values of the first scan line signal b in the given field and the next succeeding scan line signal c in that field to form a second combined scan line signal. The first and second combined scan line signals are level adjusted and added to produce an interpolated scan line signal yc;Rc-yc/Bc-yc intermediate successive main scan lines in the given field.

公开(公告)号：DE68927597D1

公开(公告)日：1997-02-13

申请号：DE68927597

申请日：1989-07-18

Applicant: SONY CORP

Inventor： MOTOE HISAFUMI ,  KAWASHIMA HIROYUKI ,  TOKUHARA MASAHARU

IPC: H04N7/01 ,  H04N11/20 ,  H04N5/44

Abstract: Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit 501y,502y,503y; 501C,502C,503C, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal b in a given field, the next succeeding scan line signal c in that field, an interlaced scan line signal a in the next succeeding field and an interlaced scan line signal d in the next preceding field. A first combining circuit 504y,504C combines the signal values of the next succeeding field interlaced scan line signal a and the next preceding field interlaced scan line signal d to form a first combined scan line signal. A second combining circuit 505y;505C combines the signal values of the first scan line signal b in the given field and the next succeeding scan line signal c in that field to form a second combined scan line signal. The first and second combined scan line signals are level adjusted and added to produce an interpolated scan line signal yc;Rc-yc/Bc-yc intermediate successive main scan lines in the given field.

公开(公告)号：DE69120770D1

公开(公告)日：1996-08-14

申请号：DE69120770

申请日：1991-10-22

Applicant: SONY CORP

Inventor： KAWASHIMA HIROYUKI ,  KITA HIROYUKI ,  OBANA SHUICHI ,  TOKUHARA MASAHARU

IPC: H04N5/46 ,  H04N7/01 ,  H04N9/64 ,  H04N5/44

Abstract: A video signal processing circuit used for such a non-interlace television comprises an interfield interpolation circuit for carrying out interfield interpolation by using a video signal before one field of an input video signal to output interpolated line video signals corresponding to respective interline positions in one field, an intrafield interpolation circuit for carrying out intrafield interpolation by using video signals of a plurality of lines of the input video signal to output interpolated line video signals corresponding to respective interline positions in one field, a motion detector for detecting motion of the input video signal, a weighting adder for implementing weighting to an output signal from the interfield interpolation circuit and an output signal from the intrafield interpolation circuit in accordance with a signal from the motion detector to add the weighted output signals, a sequential scan converter for carrying out conversion into a sequential scanning signal on the basis of the input video signal and an output signal from the weighting adder, and a controller for controlling at least the interfield interpolation means in accordance with a television standard system of the input video signal, thereby making it possible to lessen disturbance, e.g., deterioration in the picture quality, etc. occurring in the interlaced scanning.