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    Fractional frequency clock divider with direct division
    61.
    发明授权
    Fractional frequency clock divider with direct division 有权

    公开(公告)号：US10153777B2

    公开(公告)日：2018-12-11

    申请号：US15281617

    申请日：2016-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Reza Hoshyar ,  Wenting Zhou ,  Ali Kiaei ,  Baher Haroun ,  Ahmad Bahai

    IPC: H03L7/00 ,  H03L7/197 ,  H03L7/16 ,  H03L7/18

    Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

    WAVEGUIDE COUPLER
    65.
    发明申请
    WAVEGUIDE COUPLER 有权
    波形耦合器

    公开(公告)号：US20140111394A1

    公开(公告)日：2014-04-24

    申请号：US13657615

    申请日：2012-10-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Eunyoung Seok ,  Srinath Ramaswamy ,  Brian B. Ginsburg ,  Vijay B. Rentala ,  Baher Haroun

    IPC: H01Q13/00 ,  H01P11/00 ,  H01Q1/42

    CPC classification number: H01P11/001 ,  H01P5/08 ,  H01P5/107 ,  H01Q9/04 ,  H01Q9/0407 ,  H05K3/20 ,  H05K3/4038 ,  H05K3/4644 ,  Y10T29/49016

    Abstract: An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly.

    Abstract translation: 提供了一种装置。 在该装置中，存在天线封装和集成电路（IC）。 电路迹线组件固定到IC。 耦合器（具有天线组件和高阻抗表面（HIS））固定到电路迹线组件。 天线组件具有窗口区域，基本上围绕窗口区域的导电区域，与IC连通的圆形贴片天线以及位于窗口区域内的椭圆形贴片天线，其延伸至少一个 圆形贴片天线的一部分，并且与圆形贴片天线通信。 HIS基本上围绕天线组件。

    WAKEUP MECHANISM FOR AN AUDIO SYSTEM
    66.
    发明申请
    WAKEUP MECHANISM FOR AN AUDIO SYSTEM 有权

    公开(公告)号：US20250142241A1

    公开(公告)日：2025-05-01

    申请号：US18495675

    申请日：2023-10-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Udit Rawat ,  Bichoy Bahr ,  Baher Haroun

    IPC: H04R1/08

    Abstract: An acoustic device is provided which comprises an audio system including: a microphone having a microphone output, and a processing circuit having a wakeup input, an audio input, and an audio output, the audio input coupled to the microphone output. In at least one example, the acoustic device further comprises an acoustic sensor separate from the microphone, the acoustic sensor having a sensor output. In at least one example, the acoustic device further comprises a wakeup circuit having a sensor input and a wakeup output, the sensor input coupled to the sensor output, wherein the wakeup output is coupled to the wakeup input.

    BIDIRECTIONAL DATA TRANSMISSION OVER ISOLATION MEDIUM
    67.
    发明申请
    BIDIRECTIONAL DATA TRANSMISSION OVER ISOLATION MEDIUM 有权

    公开(公告)号：US20240430147A1

    公开(公告)日：2024-12-26

    申请号：US18341482

    申请日：2023-06-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tolga Dinc ,  Swaminathan Sankaran ,  Baher Haroun

    IPC: H04L27/20 ,  H04L5/14

    Abstract: An apparatus includes a controller having differential modulation control outputs and is configured to provide differential modulation signals having a particular frequency at the differential modulation control outputs. A differential modulator circuit is coupled between first differential terminals and second differential terminals. The differential modulator circuit has differential modulation control inputs coupled to the differential modulation control outputs. The differential modulator circuit is configured to: modulate first differential signals at the first differential terminals with the differential modulation signals having the particular frequency, provide the modulated first differential signals at the second differential terminals, modulate second differential signals at the second differential terminals with the differential modulation signals having the particular frequency, and provide the modulated second differential signals at the first differential terminals.

    Driver system for reducing common mode noise due to mismatches in differential signal path
    68.
    发明授权
    Driver system for reducing common mode noise due to mismatches in differential signal path 有权

    公开(公告)号：US12136918B2

    公开(公告)日：2024-11-05

    申请号：US17872841

    申请日：2022-07-25

    Applicant: Texas Instruments Incorporated

    Inventor： Srijan Rastogi ,  Sumantra Seth ,  Baher Haroun

    IPC: H03F3/45 ,  H03K3/01

    Abstract: A driver system includes a non-inverting system input, an inverting system input, a non-inverting system output and an inverting system output. The driver system includes a line driver which includes a non-inverting driver input coupled to the non-inverting system input and includes an inverting driver input coupled to the inverting system input. The line driver includes an inverting driver output and a non-inverting driver output. The driver system includes a first termination resistor coupled between the non-inverting driver output and the non-inverting system output and includes a second termination resistor coupled between the inverting driver output and the inverting system output. The driver system includes a first amplifier stage coupled to the line driver and includes a second amplifier stage coupled to the line driver.

    Charge pump
    70.
    发明授权
    Charge pump 有权

    公开(公告)号：US11411566B2

    公开(公告)日：2022-08-09

    申请号：US17397954

    申请日：2021-08-09

    Applicant: Texas Instruments Incorporated

    Inventor： Salvatore Luciano Finocchiaro ,  Tolga Dine ,  Gerd Schuppener ,  Siraj Akhtar ,  Swaminathan Sankaran ,  Baher Haroun

    IPC: H03L7/089 ,  H02M3/07 ,  H03L7/087

    Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

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