公开(公告)号：JPH0984094A

公开(公告)日：1997-03-28

申请号：JP24034095

申请日：1995-09-19

Applicant: TOSHIBA CORP

Inventor： KAMAGATA EIJI ,  SERIZAWA MUTSUMI

IPC: H04L29/00 ,  H04W4/00 ,  H04W84/00 ,  H04Q7/22 ,  H04Q7/28

Abstract: PROBLEM TO BE SOLVED: To attain rational operation by storing the state of a data storage device and a battery together with the position information of a radio terminal equipment thereby enabling a high speed communication while suppressing energy consumption. SOLUTION: A radio equipment 102 has a radio zone 108 and radio equipments 103, 104 serve radio communication for radio zones A, B in the zone 108 by a spot beam. A storage device 106 stores position information of the radio terminal equipments and the mobile terminal equipments and a call controller 105 references storage information of the device 106. An information server 107 stores various information to be served to the user of the radio terminal equipment. Furthermore, a wired communication network 101 connects to the equipments 102, 103, 104, the devices 106, 105 and the server 107 to transmit data to be communicated among the devices and the terminal equipments.

公开(公告)号：JPH08275236A

公开(公告)日：1996-10-18

申请号：JP7402695

申请日：1995-03-30

Applicant: TOSHIBA CORP

Inventor： SERIZAWA MUTSUMI ,  SHIMIZU HIDEO ,  WAKUTSU TAKASHI ,  NAKAJIMA NOBUYASU ,  OGURA KOJI ,  NOUJIN KATSUYA ,  SUGAWARA TSUTOMU

IPC: G06F13/00 ,  H04W28/06 ,  H04W28/18 ,  H04W88/02 ,  H04Q7/38

Abstract: PURPOSE: To make a processing speed required for information display by a mobile terminal equipment in the unit of pages constant apparently while keeping the communication quality constant. CONSTITUTION: In the mobile communication system where information is sent between a base station 1 and a mobile station 3 via a high speed down-link 4 and a low speed up-link 5, the base station 1 sends the information managed in the unit of pages and having a page number in each page at a variable transmission speed via the high speed down-link 4 in response to a circulation request from a terminal equipment 3. The terminal 3 sends the page number in response to the circulation indication input by the user via the low speed up-link 5 to the base station 1, and when the transmission speed of the high speed down-link 4 is a prescribed value or below, the information sent from the base station 1 via the high speed down-link 4 from the base station 1 is stored in a memory and the information of a desired page is displayed. Then, the page number of preceding and succeeding pages during the display is sent to the base station 1 as a circulation request and the information of the preceding and succeeding pages is stored in the memory.

公开(公告)号：JPH06188685A

公开(公告)日：1994-07-08

申请号：JP33464792

申请日：1992-12-15

Applicant: TOSHIBA CORP

Inventor： HAYASHI TAKAHISA ,  SERIZAWA MUTSUMI

IPC: H03H21/00 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06

Abstract: PURPOSE:To make the circuit scale small by reducing number of tap coefficients to be stored so as to reduce the capacity of a tap coefficient memory thereby reducing number of gates for circuit integration. CONSTITUTION:An initial sample a0 is sampled for each of blocks a-j of an impulse response and stored in an initial value memory 10 and each of the blocks a to j of the impulse response is sampled at an interval or 7 or 8 samples to obtain a difference among them and difference data are stored in a difference memory 20, and the initial value data and the difference value data read from the initial value memory 10 and the difference memory 20 are properly accumulated to generate a desired tap coefficient for the multiplication of the coefficients.

公开(公告)号：JPH066398A

公开(公告)日：1994-01-14

申请号：JP16443092

申请日：1992-06-23

Applicant: TOSHIBA CORP

Inventor： SOEYA MIYUKI ,  SERIZAWA MUTSUMI

IPC: H04L27/227 ,  H04L27/22

Abstract: PURPOSE:To perform demodulation processing with one bit and reduce the size by providing plural delay means and a phase comparing means and outputting respective pieces of phase difference information from a prescribed phase comparing means. CONSTITUTION:A clock generating means 7 generates a clock which has a rate higher than the symbol rate of an input signal and a 1st sampling means samples the input signal in synchronism with the clock. Then the output signal of the sampling means 1 is delayed by one symbol through a 1st delay means 2. A 2nd sampling means 4 samples the output signal of the delay means 2 and its output is delayed by a 1/4 synchronism time of the intermediate frequency of the input signal through a 2nd delay means 5. A 1st phase comparing means 3 outputs information on the phase difference between the input signal and the output signal of the delay means 2 and a 2nd phase comparing means 6 outputs the phase difference signal between the input signal and the output signal of the delay means 5. Then the demodulation processing is performed with one bit, the constitution is simplified to reduce the size of a digital part, and the power consumption is lowered.

公开(公告)号：JPH05183504A

公开(公告)日：1993-07-23

申请号：JP34743891

申请日：1991-12-27

Applicant: TOSHIBA CORP

Inventor： NOUJIN KATSUYA ,  SERIZAWA MUTSUMI

IPC: H04B7/26

Abstract: PURPOSE:To reduce the time till a mobile station detects a voiced sound till voice data are sent in the system sending the voice part of a conversation in digital mobile communication. CONSTITUTION:A base station 102 adds information of an idle slot to control information and applies multiple address communication of the resulting information to plural mobile stations 101, and after the mobile station 101 sends a slot allocation signal, the station 101 decides its own transmission slot based on the idle slot information in the control information received by the base station 101 and sends the voice signal through the slot. Thus, it is possible to reduce the time from the detection of a voiced part of the mobile station 101 till the transmission of voice data and communication with excellent quality is attained because the delay between a talker and a listener is actually reduced.

公开(公告)号：JPH04286223A

公开(公告)日：1992-10-12

申请号：JP4981291

申请日：1991-03-14

Applicant: TOSHIBA CORP

Inventor： YOSHIDA HIROSHI ,  MAEDA TADAHIKO ,  SERIZAWA MUTSUMI ,  SUZUKI YASUO

IPC: H04B7/26 ,  H04M1/00

Abstract: PURPOSE:To set a line from a call originatable terminal to a call origination exclusive terminal by combining the call originating exclusive terminal and a pager, and providing a repeating terminal having, at least, two lines. CONSTITUTION:The call originatable terminal 4 originates a call to call terminating equipment in the repeating terminal 3 through a telephone network. When the call terminating equipment receives the call from the terminal 4, it turns immediately that line into a holding state, and on the other hand, it calls the pager in a portable type terminal 1 through a pager base station 6 by automatic dialing equipment and call originating and terminating equipment by using the other line, and afterwards, it cuts off automatically the line by automatic line cut-off equipment. The pager in the portable type terminal 1 having been called from the repeating terminal originates automatically the call from the call originating only terminal to the repeating terminal 3 by the automatic dialing equipment through a radio base station 2 and a central telephone exchange 5. Thus, the line is set between the portable type terminal 1 and the repeating terminal 3.

公开(公告)号：JPH04207548A

公开(公告)日：1992-07-29

申请号：JP33562190

申请日：1990-11-30

Applicant: TOSHIBA CORP

Inventor： SOEYA MIYUKI ,  OGURA KOJI ,  SERIZAWA MUTSUMI

IPC: H04L27/14 ,  H04L27/22

Abstract: PURPOSE:To accurately detect synchronization by providing an input means, a local oscillator, a carrier frequency conversion means, a frequency offset correction means, an equalizer and a synchronization detection means to the synchronization device. CONSTITUTION:A reception signal and a signal outputted from a local oscillator 3 are inputted to a multiplier 2, in which the signal is converted into a desired intermediate frequency signal or a base band signal and it is inputted to a frequency offset detector 4. The detector 4 outputs a voltage in response to a frequency offset to the oscillator 3 to correct the frequency of the oscillator 3 so that the frequency offset is 0. A base band signal whose frequency offset is improved by the action of an AFC(Automatic Frequency Control) 10 is converted into a digital signal by an A/D converter 5, the signal is equalized and demodulated by an equalizer 6 and the demodulation data is transferred to a monitor 7. The monitor 7 compares the inputted demodulation data with a known signal and confirms it that no error is in existence, then the circuit 10 detects the synchronization. Thus, accurate synchronization is detected.

公开(公告)号：JPH0370206A

公开(公告)日：1991-03-26

申请号：JP20471289

申请日：1989-08-09

Applicant: TOSHIBA CORP

Inventor： OGURA KOJI ,  SERIZAWA MUTSUMI ,  SATO NOBUTADA

IPC: H03J7/18 ,  H04L27/22

Abstract: PURPOSE:To reduce a tracking time by repeating a series of operations selecting a frequency at which large power is provided. CONSTITUTION:A power comparator 7 outputs a result to a frequency selection circuit 10 as to whether selected power is stored in a memory 8 or outputted from a power calculator 6. The frequency selection circuit 10 decides the succeeding frequency based on the information from the power comparator 7 to change the frequency in a local oscillator 2. Then a power when a frequency of the local oscillator 2 is f3 being a median of frequencies f1, f2 and a power stored in the memory 8 when the frequency is f2 are compared and the power when the frequency is f3 close to the f0 is selected. The operation is repeated and the frequency f5 closest to the frequency f0 is detected as an offset. Thus, it is not required to sweep all ranges of possible frequency offset and the tracking time of the frequency is reduced without the deterioration of accuracy.

公开(公告)号：JPH02262734A

公开(公告)日：1990-10-25

申请号：JP8143389

申请日：1989-04-03

Applicant: TOSHIBA CORP

Inventor： OGURA KOJI ,  SERIZAWA MUTSUMI

IPC: H04J1/00 ,  H04J11/00

Abstract: PURPOSE:To realize the miniaturization of a device and the simplification of a channel separation processing which perform the separation and the demodulation of a channel by using a multiplier that is one of constituents provided at every channel and a memory commonly to each channel. CONSTITUTION:A reception signal is inputted to the multipliers 1 and 2, and the output of an in-phase component and that of an orthogonal component can be obtained, and they are A/D-converted by A/D converters 7 and 8, then, inputted to the multipliers 9 and 10, and the multipliers 11 and 12, respectively. The output of the multipliers 9 and 11 are subtracted by a subtractor 15, and that of the multipliers 10 and 12 are added by an adder 13, and only low frequency band areas are outputted by low-pass filters 20 and 21, then, the in-phase component 1 and the orthogonal component 2 can be obtained. Similarly, the output of the multipliers 10 and 12 are subtracted by a subtractor 14, and that of the multipliers 9 and 11 are added by an adder 16, then, the in-phase component 3 and the orthogonal component 4 can be obtained via low-pass filters 22 and 23.

公开(公告)号：JPH02149048A

公开(公告)日：1990-06-07

申请号：JP30268388

申请日：1988-11-30

Applicant: TOSHIBA CORP

Inventor： SERIZAWA MUTSUMI ,  MURAKAMI JUNZO

IPC: H04L27/227 ,  H04L27/22

Abstract: PURPOSE:To make a device operate favorably under low S/N, and to make a phase following characteristic good by estimating a transmission signal by comparing the states from the past to the present of the amplitude and the phase of a reception signal and the states from the past to the present of the amplitude and the phase of a reference signal. CONSTITUTION:A comparing means 63 is constituted of a delay and conjugate operating part 59 consisting of a delay circuit 67 and a conjugate operating part 69, a reference signal generating part 71, a subtracter 73 and the square operating part 75 of an absolute value. A maximum likelihood estimating means 65 is provided with a viterbi algorithm operating part 77. The subtracter 73 obtains difference between the reference signal outputted from the reference signal generating part 71 and the output signal of a multiplier 61. The square operating part 75 of the absolute value calculates the square of the absolute value of the output signal of the subtracter 73 as a branch metric. The viterbi algorithm operating part 77 executes the maximum likelihood estimation for the branch metric i.e., the output signal of the square operating part 75 by viterbi algorithm, and outputs decoded data.