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公开(公告)号：JP2006019006A
公开(公告)日：2006-01-19
申请号：JP2005189888
申请日：2005-06-29
Inventor： FREY CHRISTOPHE
IPC: G11C11/15 , H01L21/8246 , H01L27/105
CPC classification number: G11C11/16 , G11C11/5607
Abstract: PROBLEM TO BE SOLVED: To provide a magnetic random access memory element which can store multi-bits.
SOLUTION: The magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines , the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store within the element in any one of at least three logic states.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供可以存储多位的磁性随机存取存储元件。 解决方案：磁性随机存取存储元件由第一磁性隧道结和第二磁性隧道结构成。 这些磁性隧道结在串联电阻电路中相互连接。 连接的第一和第二磁性隧道结通过存取晶体管连接到位线。 写入位线和写入数据线与第一和第二磁性隧道结中的每一个相关联。 通过向这些线路施加适当的电流，可以控制与第一和第二磁性隧道结中的每一个的磁矢量取向，以便以至少三个逻辑状态中的任何一个存储在元件内。 版权所有（C）2006，JPO＆NCIPI
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62.发明专利Apparatus and method using hashing for efficiently implementing ip lookup solution in hardware 审中-公开使用HASHING有效地实现硬件中的IP查找解决方案的装置和方法
公开(公告)号：JP2005198285A
公开(公告)日：2005-07-21
申请号：JP2004374336
申请日：2004-12-24
Inventor： RAJGOPAL SURESH , HUANG LUN-BIN , RICHARDSON NICHOLAS
CPC classification number: H04L45/00 , H04L45/745 , H04L45/7453 , H04L45/7457 , H04L49/25 , H04L49/55
Abstract: PROBLEM TO BE SOLVED: To provide an advanced IP address lookup technology. SOLUTION: Internet Protocol address prefixes are hashed into hash tables allocated memory blocks on demand after collisions occur for both a first hash and a single rehash. The number of memory blocks allocated to each hash table is limited, with additional prefixes, handled by an overflow content addressable memory. Each hash table contains only prefixes of a particular length, different hash tables contain prefixes of different lengths. Only subset of possible prefix lengths are accommodated by the hash tables, a remainder of prefixes is handled by the content addressable memory or a similar alternate address lookup facility. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供高级IP地址查找技术。 解决方案：互联网协议地址前缀在哈希表中被散列成分配的内存块，在第一个哈希和单个重新发生冲突之后也可以。 分配给每个哈希表的存储器块的数量受限于额外的前缀，由溢出内容可寻址存储器处理。 每个散列表仅包含特定长度的前缀，不同的散列表包含不同长度的前缀。 只有哈希表容纳了可能的前缀长度的子集，剩余的前缀由内容可寻址存储器或类似的备用地址查找工具来处理。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005182989A
公开(公告)日：2005-07-07
申请号：JP2004365219
申请日：2004-12-17
Inventor： WORLEY JAMES L
CPC classification number: H03M13/095
Abstract: PROBLEM TO BE SOLVED: To provide technique for performing error correction and error detection on a wide data word in a memory system and other systems including a memory.
SOLUTION: A parity generation circuit includes a plurality of bit generation circuits. Each of the bit generation circuits operates to receive each data bit and each hard latch signal, and generate a parity signal indicating the parity of the corresponding data bit when the hard latch signal is inactive. Each of the bit generation circuits drives the parity signal to a setting value when the hard latch signal is active. An output circuit is coupled with a bit generation circuit to receive the parity signal, and operates to generate an output parity signal in response to the parity signal from the bit generation circuit.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供对存储器系统和包括存储器的其他系统中的宽数据字执行纠错和错误检测的技术。 解决方案：奇偶产生电路包括多个位产生电路。 每个位产生电路操作以接收每个数据位和每个硬锁存信号，并且当硬锁存信号不活动时，产生指示相应数据位的奇偶性的奇偶校验信号。 当硬锁存信号有效时，位产生电路中的每一个将奇偶校验信号驱动到设定值。 输出电路与位生成电路耦合以接收奇偶信号，并且响应于来自位产生电路的奇偶校验信号而操作以产生输出奇偶校验信号。 版权所有（C）2005，JPO＆NCIPI
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64.发明专利Integrated and released beam layer structure manufactured in trench and its manufacturing method 有权一体化和释放的梁结构在TRENCH中制造及其制造方法
公开(公告)号：JP2005169616A
公开(公告)日：2005-06-30
申请号：JP2004340417
申请日：2004-11-25
Inventor： BLANCHARD RICHARD A , MCALEXANDER JOSEPH C
IPC: G01P15/135 , B81B3/00 , B81C1/00 , G01K5/62 , G01P15/18
CPC classification number: B81C1/00626 , B81B2201/0235 , B81B2203/0118 , B81B2203/033 , B81C2201/0109 , B81C2201/014
Abstract: PROBLEM TO BE SOLVED: To provide an integrated and released beam layer structure manufactured in a trench and its manufacturing method.
SOLUTION: The beam layer structure has a semiconductor substrate 20, the trench 18, a first electrical conducting layer 24, and the beam 28. The trench is extended inside the semiconductor substrate and has a wall. The first electrical conducting layer is positioned on the wall of the trench in the selected position. The beam is positioned on the trench, and the first part of it is connected to the semiconductor substrate, and a second part of it is movable. The second part of the beam is separated from the wall of the trench by the selected distance. Therefore, the second part of the beam is freely movable inside the plane vertical or parallel to the surface of the substrate, and can be deflected, that is, deformed relative to the trench so as to electrically contact in response to a predetermined acceleration force applied to the beam structure or the change of a predetermined temperature.
COPYRIGHT: (C)2005,JPO&NCIPIAbstract translation: 要解决的问题：提供在沟槽中制造的集成和释放的束层结构及其制造方法。 解决方案：光束层结构具有半导体衬底20，沟槽18，第一导电层24和光束28.沟槽在半导体衬底的内部延伸并具有壁。 第一导电层位于选择位置的沟槽壁上。 光束定位在沟槽上，其第一部分连接到半导体衬底，其第二部分是可移动的。 梁的第二部分与沟槽的壁分开一定距离。 因此，梁的第二部分可以在垂直或平行于基板的表面的平面内自由移动，并且可以被偏转，即相对于沟槽变形，以便响应于施加的预定加速力而电接触 到梁结构或预定温度的变化。 版权所有（C）2005，JPO＆NCIPI
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公开(公告)号：JP2005135574A
公开(公告)日：2005-05-26
申请号：JP2004312044
申请日：2004-10-27
Inventor： MA HERMAN
IPC: G11C13/00 , G11C16/02 , G11C16/26 , H01L27/105 , H01L27/10
CPC classification number: G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/79
Abstract: PROBLEM TO BE SOLVED: To provide an improved semiconductor memory device in which comparatively high-speed phase change material is used. SOLUTION: The device is a circuit and a method for the memory device for a phase change memory, and the like. A memory 1 having a plurality of columns of a memory cells 2 is especially provided, and each column of the memory cells is connected to a bit line 4 or a data line. Each of the memory cells includes a programmable resistance element connected in series to a selection transistor. Each of the bit lines is connected to a separate reference cell and a separate transistor. The transistor is connected between the corresponding bit line and reference voltage such as grounding, and the like. During the period of the memory read operation, the transistor, the reference cell and the addressed memory cell form a differential amplifier circuit. Output from the differential amplifier circuit is connected to a data output terminal for the phase change memory. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 解决的问题：提供一种使用比较高速的相变材料的改进的半导体存储器件。 解决方案：该装置是用于相变存储器的存储装置的电路和方法等。 特别提供具有存储单元2的多列的存储器1，并且每列存储单元连接到位线4或数据线。 每个存储单元包括与选择晶体管串联连接的可编程电阻元件。 每个位线连接到单独的参考单元和单独的晶体管。 晶体管连接在相应的位线和参考电压如接地等之间。 在存储器读取操作期间，晶体管，参考单元和寻址的存储单元形成差分放大器电路。 差分放大电路的输出与相变存储器的数据输出端子连接。 版权所有（C）2005，JPO＆NCIPI
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Patent Agency Ranking
公开(公告)号：JP2005065491A
公开(公告)日：2005-03-10
申请号：JP2004231534
申请日：2004-08-06
Inventor： SHAO JIANWEN , HOPKINS THOMAS L
Abstract: PROBLEM TO BE SOLVED: To provide a technique to determine the direction of rotation of a sensorless motor operating in the state of freewheel, by comparing signals induced in a motor winding. SOLUTION: A device and method for determining the freewheel rotation of an electric motor is provided comprises a step to measure first and second signals from first and second windings of an unenergized motor, respectively, and a step to determine whether or not an energized motor is rotating from the first and second signals. The method can also determine the direction of rotation from the first and second signals when the unenergized motor is rotating. Further the method can measure a third signal from a third winding of the unenergized motor, and when determining whether or not the motor is rotating the method can determine that the motor is not rotating if the first, second and third signals are equal. Each of the first and second signals can have a back-voltage. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：通过比较在电动机绕组中感应的信号，提供一种确定在自由轮状态下工作的无传感器电动机的旋转方向的技术。 解决方案：提供一种用于确定电动机的自由轮旋转的装置和方法，包括分别测量未通电电动机的第一和第二绕组的第一和第二信号的步骤，以及确定是否 通电电动机从第一和第二信号旋转。 该方法还可以在非电动马达旋转时从第一和第二信号确定旋转方向。 此外，该方法可以测量来自未通电电动机的第三绕组的第三信号，并且当确定电动机是否旋转时，如果第一，第二和第三信号相等，则该方法可以确定电动机不旋转。 第一和第二信号中的每一个可以具有反向电压。 版权所有（C）2005，JPO＆NCIPI
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67.发明专利System and method for simulating universal serial bus smart card device connected to usb host 审中-公开用于模拟连接到USB主机的通用串行总线智能卡设备的系统和方法
公开(公告)号：JP2004280818A
公开(公告)日：2004-10-07
申请号：JP2004069739
申请日：2004-03-11
Inventor： TOURNEMILLE JEROME , TAMAGNO DAVID
CPC classification number: G06F17/5022
Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for simulating a USB smart card. SOLUTION: The system and the method for simulating a universal serial bus (USB) smart card device connected with a USB host device for development and debugging are provided and it includes a computer simulator and a USB host device with a host controller operatively connected along a communication link with the computer simulator for transmitting or receiving data packets to or from the computer simulator. A microcontroller is located between the computer simulator and the USB host device and translates the data packets into a USB protocol used by the USB host device and defined by the computer simulator. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供用于模拟USB智能卡的系统和方法。 解决方案：提供了用于模拟与USB主机设备进行开发和调试的通用串行总线（USB）智能卡设备的系统和方法，并且其包括计算机模拟器和具有主机控制器的USB主机设备 沿着与计算机模拟器的通信链路连接，用于向计算机模拟器发送数据分组或从计算机模拟器接收数据分组。 微控制器位于计算机模拟器和USB主机设备之间，并将数据分组转换为由USB主机设备使用并由计算机模拟器定义的USB协议。 版权所有（C）2005，JPO＆NCIPI
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68.发明专利
公开(公告)号：JP2004228089A
公开(公告)日：2004-08-12
申请号：JP2004013433
申请日：2004-01-21
Inventor： LO PRIORE STEFANO , PALMIERI MICHELE , MASTROMATTEO UBALDO
CPC classification number: H01M8/241 , H01M4/8626 , H01M8/0247 , H01M8/1007 , Y02P70/56
Abstract: PROBLEM TO BE SOLVED: To provide a micro fuel cell capable of supplying sufficient power while maintaining structural reliability, and a method of manufacturing the same. SOLUTION: The micro fuel cell 30 includes a substrate 32 and a plurality of outwardly extending PEM separators 34 spaced from each other to define positive and negative micro fluid channels 36 and 38. A positive catalyst/electrode serves as the lining of at least part of the positive micro fluid channel 36, and a negative catalyst/electrode serves as the lining of at least part of the negative micro fluid channel 38. COPYRIGHT: (C)2004,JPO&NCIPI
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公开(公告)号：JP2004194343A
公开(公告)日：2004-07-08
申请号：JP2003415101
申请日：2003-12-12
Inventor： HUANG LUN BIN , RICHARDSON NICHOLAS , RAJGOPAL SURESH
IPC: H04L12/56
CPC classification number: H04L45/00 , H04L45/54 , H04L45/7457
Abstract: PROBLEM TO BE SOLVED: To provide a path compression optimization system and method therefor. SOLUTION: The path optimization system and method for eliminating single entry trie tables, which are used in a pipeline network search engine of a router, are provided. This system embeds in a parent trie table (1) path compression patterns having common prefix bits of a data packet and (2) skip counts indicating the length of the path compression patterns. The network search engine uses the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses required for traversing the data structure. COPYRIGHT: (C)2004,JPO&NCIPI
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公开(公告)号：JP2004194319A
公开(公告)日：2004-07-08
申请号：JP2003408480
申请日：2003-12-08
Inventor： HUANG LUN BIN , RICHARDSON NICHOLAS , RAJGOPAL SURESH
CPC classification number: H04L45/54
Abstract: PROBLEM TO BE SOLVED: To provide an improved multi-bit trie network search engine and an operating method thereof. SOLUTION: The multi-bit trie network search engine is realized by the number of pipeline logic units corresponding to the number of longest prefix strides, and a combination of memory blocks for holding prefix tables. Each of the pipeline units is limited to one memory access, and the end point within the pipeline logic unit chain is variable to deal with prefixes having different lengths. The memory blocks are coupled to the pipeline logic units by a mesh type crossbar and form a combination of virtual memory banks, and memory blocks in arbitrary given physical memory banks may be allocated to a virtual memory bank for arbitrary specified pipeline logic unit. An embedded type programmable processor manages insertion and deletion of route in the prefix tables together with configuration of the virtual memory banks. COPYRIGHT: (C)2004,JPO&NCIPI
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