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    MONITORING LINE CONDITIONS IN THE DATA TRANSMISSION MODE
    61.
    发明授权
    MONITORING LINE CONDITIONS IN THE DATA TRANSMISSION MODE 失效
    在线监测DATENÜBERTRAGUNGSSMODUS

    公开(公告)号：EP0980606B1

    公开(公告)日：2004-11-17

    申请号：EP98922123.9

    申请日：1998-05-06

    Applicant: Legerity, Inc.

    Inventor： YIP, Phillip, C. ,  RAHMATULLAH, Muhammad, M. ,  COLE, Terry, L.

    IPC: H04L1/24

    CPC classification number: H04L1/242 ,  H04L1/241

    Abstract: A method and apparatus for allowing a modem transmitting data in the data mode to initiate retraining mode due to changing line conditions. The modem inserts a test signal within the data received from a computer system. The data and test signal are encoded and sent over a network to a second modem. The second modem compares the test signal with a standard test signal, and if the test signal received is different from the standard test signal, the second modem initiates retraining of the modems to adjust for the varying line conditions.

    System and method for determining on-chip bit error rate (BER) in a communication system
    62.
    发明公开
    System and method for determining on-chip bit error rate (BER) in a communication system 审中-公开
    系统与Verfahren zur Ermittlung der in-chip-Bitfehlerrate（BER）in einem Kommunikationssystem

    公开(公告)号：EP1388969A2

    公开(公告)日：2004-02-11

    申请号：EP03018065.7

    申请日：2003-08-07

    Applicant: Broadcom Corporation

    Inventor： Fan, Nong ,  Hoang, Tuan ,  Jiang, Hongtao

    IPC: H04L1/24

    CPC classification number: H04L1/243 ,  H04L1/203 ,  H04L1/241

    Abstract: A test packet generator (225a) within a physical layer device (230) may generate test packets to be communicated over a closed communication path established within the physical layer device (230). The test packets may include a pseudo-random bit sequence. A receiver within the physical layer device (230) may receive at least a portion of the generated test packet. A test packet checker (225b) within the physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine the bit error rate for the physical layer device. A window counter (225c) within the physical layer device (230) may count at least a portion of a number of bits received within the generated test packets and a number of bits that are in error in at least a portion of the number of bits received. Accordingly, the bit error rate may be calculated based on a ratio of the number of counted bits in error to the number bits counted in the at least a portion of the number of bits received.

    Abstract translation: 物理层设备（230）内的测试分组生成器（225a）可以生成要通过在物理层设备（230）内建立的封闭通信路径进行通信的测试分组。 测试分组可以包括伪随机比特序列。 物理层设备（230）内的接收器可以接收生成的测试分组的至少一部分。 物理层设备内的测试分组检查器（225b）可以将所接收的测试分组的至少一部分与生成的测试分组的至少一部分进行比较，以便确定物理层设备的误码率。 物理层设备（230）内的窗口计数器（225c）可以对生成的测试分组内接收的多个比特的数量的至少一部分进行计数，并且在比特数的至少一部分中计数出错误的比特数 接收。 因此，可以基于错误的计数比特数与在所接收的比特数的至少一部分中计数的数量比的比率来计算误码率。

    Advanced code error detection apparatus and system using maximal-length pseudorandom binary sequence
    64.
    发明公开
    Advanced code error detection apparatus and system using maximal-length pseudorandom binary sequence 失效
    装置用于误差检测和装置，其具有最大长度的二进制伪随机序列。

    公开(公告)号：EP0523571A1

    公开(公告)日：1993-01-20

    申请号：EP92111828.7

    申请日：1992-07-10

    Applicant: ANRITSU CORPORATION

    Inventor： Ajima, Hiroyuki ,  Ishiyama, Nobuki ,  Hattori, Tsukasa

    IPC: H04L1/24

    CPC classification number: H03M13/37 ,  H04L1/241 ,  H04L1/242

    Abstract: A switching circuit (8) switches operation states between a state in which m consecutive bit data of an M-sequence reception code having a period (2 m - 1), which is input to a measurement terminal (7), are set in a feedback shift register (FSR) (9), and a state in which the FSR (9) is set in a closed-loop state to be set in a self-running state. A synchronization detection comparator (10) sequentially compares each bit data output from the FSR (9) in a self-running state with corresponding bit data of the reception code. On the basis of the comparison result from the synchronization detection comparator (10), a control section (15) determines that the bit data output from the FSR (9) are a reference code, or outputs a command to the FSR (9) through the switching circuit (8) to fetch the m bit data again. A storage circuit (18) stores consecutive bit data of the reception code which are input before the control section determines that the bit data are the reference code, and outputs the stored bit data upon delaying them by a predetermined period of time. A bit error detection comparator (19) sequentially compares the bit data of the delayed reception code output from the storage circuit (18) with the bit data output from the FSR (9) and determined as the reference code.

    Abstract translation: 开关电路（8）开关的状态之间的操作状态，其中M具有周期的M-序列的接收码连续比特数据（2 - 1），所有这些被输入到测量端子（7），被设定 在一个反馈移位寄存器（FSR）（9），并且其中FSR（9）在闭环状态被设定的状态下，以在自运行状态来设定。 同步检测比较器（10）顺序地比较各比特数据输出从FSR（9）转换为自运行状态与接收码的对应位的数据。 从同步检测比较器（10）的比较结果的基础上，控制部（15）bestimmt，从FSR（9）是一个参考码输出DASS模具位数据，或命令输出到FSR（9）通过 开关电路（8），以再次获取的m位数据。 存储电路（18）存储接收码的连续位数据哪些是控制部bestimmt之前输入，DASS模具位数据是参考代码，并经一预定的时间周期延迟他们存储的位数据输出。 一种误码检测比较器（19）顺序地比较从与来自FSR（9）和确定性开采作为基准码输出的比特数据的存储电路（18）输出的延时的接收码的位数据。

    Receiver clock test circuitry and related methods and apparatuses
    66.
    发明授权
    Receiver clock test circuitry and related methods and apparatuses 有权

    公开(公告)号：US09906335B2

    公开(公告)日：2018-02-27

    申请号：US15361152

    申请日：2016-11-25

    Applicant: Rambus Inc.

    Inventor： Srinivasaraman Chandrasekaran ,  Kunal Desai

    IPC: H03H7/30 ,  H04L1/20 ,  H04L7/00 ,  H04L7/10

    CPC classification number: H04L1/205 ,  G01R31/31709 ,  G01R31/31726 ,  H04L1/241 ,  H04L1/242 ,  H04L7/0079 ,  H04L7/0083 ,  H04L7/10

    Abstract: An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

    System and method for parallel testing of multiple data packet signal transceivers
    69.
    发明授权
    System and method for parallel testing of multiple data packet signal transceivers 有权
    用于并行测试多个数据包信号收发器的系统和方法

    公开(公告)号：US08842549B2

    公开(公告)日：2014-09-23

    申请号：US13716369

    申请日：2012-12-17

    Applicant: Litepoint Corporation

    Inventor： Christian Volf Olgaard ,  Ruizu Wang ,  Erdem Serkan Erdogan ,  Mathew Philip

    IPC: H04W24/00 ,  H04L12/26

    CPC classification number: H04W24/00 ,  H04L1/1867 ,  H04L1/241 ,  H04L43/50 ,  H04W24/06

    Abstract: System and method for facilitating testing of multiple data packet signal transceivers involving data-packet-signal replication and one or more status signals indicating successful and unsuccessful receptions of confirmation signals. Based upon the one or more status signals, one or more control signals cause the replicated data packet signals to be distributed to the devices under test (DUTs) such that, following successful and unsuccessful receptions of confirmation signals, corresponding replicated data packet signals are caused to fail to conform in part or to conform, respectively, with a predetermined data packet signal standard.

    Abstract translation: 涉及涉及数据分组信号复制的多个数据分组信号收发机的测试的系统和方法以及表示确认信号的成功和不成功接收的一个或多个状态信号。 基于一个或多个状态信号，一个或多个控制信号使得复制的数据分组信号被分配到被测设备（DUT），使得在成功和不成功接收到确认信号之后，引起相应的复制数据分组信号 分别不符合预定的数据分组信号标准。

    CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA
    70.
    发明申请
    CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA 有权
    发送运行长度有限数据中的分类错误

    公开(公告)号：US20140223270A1

    公开(公告)日：2014-08-07

    申请号：US13761427

    申请日：2013-02-07

    Applicant: LSI CORPORATION

    Inventor： Coralyn S. Gauvin ,  Gabriel L. Romero

    IPC: G06F11/08

    CPC classification number: G01R31/3193 ,  G06F11/076 ,  G06F11/0763 ,  G06F11/08 ,  G06F11/277 ,  H04L1/241

    Abstract: A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.

    Abstract translation: 测试模式使用游程长度限制行编码来编码以产生编码的数据块。 编码的数据块通过信道发送。 在发送数据中的最大长度运行之后的所接收的数据块中的多个比特与预期的多个比特进行比较。 基于预期的多个比特和接收的数据块中的多个比特之间的不匹配来分类一种比特错误。

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