公开(公告)号：GB2304946B

公开(公告)日：1999-11-03

申请号：GB9617595

申请日：1996-08-22

Applicant: HYUNDAI ELECTRONICS AMERICA ,  ODEUM MICROSYSTEMS INC ,  OAK TECHNOLOGY INC

Inventor： PINEDA JUAN

IPC: G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  H04N7/30

Abstract: A fast and efficient implementation of the inverse discrete cosine transform (IDCT). The disclosed IDCT processor achieves a good balance between efficient VLSI implementation and number of needed arithmetic operations and is thus particularly useful in real-time speech and video decompression applications. A standard IDCT computation is modified by factoring an IDCT formula into two parts: a prescaling of each input value followed by a multiplication with a matrix specially chosen so that the product will represent the IDCT of the input data. The premultiply constants are chosen so that the specially chosen matrix has a limited number of distinct values. The VLSI implementation of the matrix multiplication is thus greatly simplified.

公开(公告)号：DE69512142D1

公开(公告)日：1999-10-21

申请号：DE69512142

申请日：1995-06-22

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： ANDERSON MICHAEL B ,  GASPARIK FRANK

IPC: H03K3/0231 ,  H03K3/03 ,  H03L7/099 ,  H03L7/10

Abstract: The invention provides for a circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, such a VCO which also exhibits a multi-range operation is described. Range extension is achieved by modifying the delay cell (58) of a current controlled ring oscillator. The VCO transfer characteristic is linearized by piece-wise linear current control (50,52,54,56) added to the delay cell (58). Additionally, a VCO capable of multi-range operation can be provided. With the addition of multiple current sources which control booster inverter current, and by selectively enabling the additional current sources, a VCO with multiple frequency ranges can be achieved.

公开(公告)号：FR2758034B1

公开(公告)日：1999-08-27

申请号：FR9716504

申请日：1997-12-24

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： KING MERRILL K

IPC: H04Q3/00 ,  H04L12/56 ,  H04Q11/04

Abstract: A transmit scheduler maps connections to scheduled time slots in an ATM network in such a manner that minimizes burstiness in an output cell stream. The smoothness in the resulting cell streams reduces the probability of loss in the network and also assures that a connection does not exceed a preestablished bandwidth. The invention can be utilized with service with a constant bit rate (CBR), a variable bit rate (VBR) and an available bit rate (ABR) traffic. Bandwidth factors are established for cells to be transmitted as a percentage of total bandwidth of the ATM network. Lists are maintained for cells to be transmitted with each list assigned a bandwidth factor. The total bandwidth in the ATM network is apportioned into time slots according to established bandwidth factors and with different bandwidths being multiplexed across the total bandwidth. Cells are selected for transmission from the list of cells in accordance with available time slots and the bandwidth factors thereof.

公开(公告)号：DE69130933T2

公开(公告)日：1999-08-05

申请号：DE69130933

申请日：1991-06-12

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： BITTING RICKY F

IPC: H03M1/14 ,  H03M1/38 ,  H03M1/46 ,  H03M1/68 ,  H03M1/76 ,  H03M1/80

公开(公告)号：DE69130933D1

公开(公告)日：1999-04-08

申请号：DE69130933

申请日：1991-06-12

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： BITTING RICKY F

IPC: H03M1/14 ,  H03M1/38 ,  H03M1/46 ,  H03M1/68 ,  H03M1/76 ,  H03M1/80

公开(公告)号：DE3588185T2

公开(公告)日：1998-12-17

申请号：DE3588185

申请日：1985-08-07

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS INC

Inventor： MAHERAS GEORGE ,  HAYWORTH HUBERT O ,  GULETT MICHAEL R

IPC: G03F7/26 ,  G03C1/00 ,  G03C1/72 ,  G03C5/00 ,  G03C5/08 ,  G03F7/00 ,  G03F7/095 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/30

公开(公告)号：HK1002943A1

公开(公告)日：1998-09-25

申请号：HK98101983

申请日：1998-03-10

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS INC

Inventor： CRAFTS HAROLD S

IPC: H03K19/00 ,  H03K19/0185 ,  H03K ,  H03H

Abstract: An I/O transceiver circuit, suitable for use on each integrated circuit of a multi-chip module, controls the output resistance of the transmitter portion (20). Control of the output resistance is achieved by a phase-locked-loop arrangement which includes a phase detector (102) a charge pump (106), a low-pass filter (108), a voltage controller (110) and a voltage controlled oscillator (120). Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors.

公开(公告)号：FR2758037A1

公开(公告)日：1998-07-03

申请号：FR9716624

申请日：1997-12-29

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： WILLS JEFFREY MERLIN

IPC: H04L12/46 ,  H04L12/851 ,  H04Q3/00 ,  H04L29/06 ,  H04L12/66 ,  H04L12/56 ,  H04B10/12

Abstract: Switch architecture is provided for interfacing a high speed broad bandwidth communication network to a communication fabric having a bandwidth which is a fraction of the high speed broad bandwidth with the network and the fabric having different data packet formats. A multiplex/inverse multiplex unit is provided for converting data packets at the first carrier rate and in the first format to data packets in the second format, and a switch converter then converts the data packet headers in the second format into switch format headers for transmission of the data packets through ports of the communication fabric. A splitter receives the data packets from the switch converter and routes the data packets to one of a plurality of the fabric ports in accordance with the connection identifier in the switch format header, the data packets to one of a plurality of fabric ports being at a second carrier rate. A sequencer receives data packets from a plurality of fabric ports at the second carrier rate and includes a resequencing circuit for split data packets received from the plurality of fabric ports. A second switch converter converts the data packet headers received from the sequencer into data packet headers in the second format, and the second format converter receives and converts the data packets from the second switching converter at the second carrier rate into data packets in the first format and at the first carrier rate. The multiplex/inverse multiplex unit can be used to adapt any high rate data stream to a lower rate switch fabric data stream.

公开(公告)号：CA2224753A1

公开(公告)日：1998-06-30

申请号：CA2224753

申请日：1997-12-12

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： WILLS JEFFREY MERLIN

IPC: H04Q3/00 ,  H04L12/56 ,  H04Q11/04

Abstract: -14- An ATM switch with a switch queuing system which minimizes cell loss for bursty traffic, while avoiding delay for time-critical. The switch has a plurality of input ports and a plurality of output ports, a switch fabric transmitting cells from the input ports to the output ports, and a backpressure signal circuit connected between each output buffer of each output port and each input buffer of each input port. Each input port has an input buffer holding ATM cells when the cells arrive faster from the port's input channel than the input port can transmit. The input port transmits cells from its input buffer responsive to a plurality of priority levels. Each output port has an output buffer holding cells when the cells arrive faster from the input ports than the output port can transmit. The output port also transmits cells from its output buffer responsive to a plurality of priority levels. The backpressure signal circuit sends a signal from a congested output buffer through the switch fabric to those input port buffers which had immediately transmitted a cell to the output buffer so that the input port buffers cease transmission. In this manner, the ATM switch drops cells on a per-connection basis, rather than on cell priority level.

公开(公告)号：AU692448B2

公开(公告)日：1998-06-11

申请号：AU6916994

申请日：1994-05-20

Applicant: TV COM TECHNOLOGIES INC A CALI ,  HYUNDAI ELECTRONICS AMERICA A

Inventor： BECKER DONALD W ,  HARRIS FRED ,  TIERNAN JAMES C

IPC: H04L27/38 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L27/22

Abstract: A digital receiver (20) includes a tuner (24) and a demodulator (30) that obtains a baseband signal (36) carried in a received analog signal (22). A first sampler (46) operates at a preselected fixed asynchronous sampling rate on the baseband component to produce a first sampler output (48). A controllable digital filter (50) resamples the first sampler output to produce a filter output with a selectable resampling rate. The resampled output is time-position locked to baseband signal epochs. The resampling is processed to ascertain the bit stream of the baseband signal. The controllable filter sampling rate is automatically varied to correspond to the data rate of the baseband signal, so that the sampling rate of the first sampler need not change. Initial signal acquisition is achieved by operating the receiver as a frequency spectrum analyzer. A single signal-carrying band (66) is identified and demodulated, and a menu (72) carried on a transport layer (68) is read. This menu provides the center frequencies and bandwidths for all of the signals within an available frequency range, so that the receiver can be reconfigured for any desired signal. Changes in transmission characteristics of the signal can later be accommodated seamlessly by reading a change notice (74) transmitted in the transport layer and reconfiguring the receiver for the new transmission characteristics.