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    Nonvolatile memory, IC card and data processing system
    71.
    发明申请
    Nonvolatile memory, IC card and data processing system 有权

    公开(公告)号：US20030206444A1

    公开(公告)日：2003-11-06

    申请号：US10424943

    申请日：2003-04-29

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Yuki Matsuda ,  Kenya Otani ,  Minoru Kato ,  Takeo Kon

    IPC: G11C016/10

    CPC classification number: G11C16/32 ,  G11C16/30

    Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

    Method of manufacturing semiconductor device
    72.
    发明申请
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20020182847A1

    公开(公告)日：2002-12-05

    申请号：US10197411

    申请日：2002-07-18

    Applicant: Hitachi, Ltd. And Hitachi ULSI Systems Co., Ltd.

    Inventor： Natsuki Yokoyama ,  Masakazu Kawano

    IPC: H01L021/4763

    CPC classification number: H01L21/28518 ,  H01L21/28556 ,  H01L21/76877

    Abstract: A layer comprising a second metal silicide as a major constituent element or a layer comprising a second metal as a major constituent element is formed simultaneously by one single chemical vapor deposition process to the bottom surface of two out of there groups of openings etched in a dielectric film on a substrate. A surface comprising silicon as a major constituent element is exposed at each bottom (nullthrough holes or local interconnection holesnull) of the first group of openings, a surface comprising a first metal silicide as a major constituent element is exposed at each bottom of the second group of openings, and a surface comprising a first metal as a major constituent element is exposed at each bottom of the third group of openings. The manufacturing method provides low contact resistance and sufficiently small junction leakage current from a diffusion layer in connection with plugs or local interconnections, even if the etched area of the openings are of different depths, shapes, or sizes.

    Abstract translation: 包含第二金属硅化物作为主要构成元素的层或包含第二金属作为主要构成元素的层通过一个单一化学气相沉积工艺同时形成到蚀刻在电介质中的两组开口的底表面 薄膜在基材上。 包含硅作为主要构成元件的表面在第一组开口的每个底部（“通孔或局部互连孔”）处露出，包括作为主要构成元件的第一金属硅化物的表面在 第二组开口，并且包括第一金属作为主要构成元件的表面暴露在第三组开口的每个底部。 该制造方法即使蚀刻的开口区域具有不同的深度，形状或尺寸，也提供了与插头或局部互连相关联的来自扩散层的低接触电阻和足够小的结漏电流。

    Electronic Apparatus
    75.
    发明申请
    Electronic Apparatus 有权
    电子仪器

    公开(公告)号：US20130145084A1

    公开(公告)日：2013-06-06

    申请号：US13692506

    申请日：2012-12-03

    Applicant: Hitachi ULSI Systems Co., Ltd.

    Inventor： Ayumi HIROMATSU ,  Masahiro KATAYAMA ,  Takanaga YAMAZAKI

    IPC: G06F12/02 ,  H04L7/033

    CPC classification number: G06F12/0246 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0262 ,  H04L25/38

    Abstract: An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register.

    Abstract translation: 提供了具有实现高精度的波特率调整的串行通信电路的电子设备。 例如，通过时钟计数器测量接收到的串行数据中的多个比特的比特宽度，并且计算其宽度的平均值来检测其最大值和最小值。 此外，例如，最大公差和最小公差被计算为基本上为平均值的1.5倍的值和基本上为平均值的0.5倍的值，并且确定最大值和最小值是否为 在最大公差和最小公差之间的范围内。 如果它们在范围内，则在波特率设置寄存器中设置相应的平均值。

    Semiconductor integrated circuit device
    77.
    发明申请
    Semiconductor integrated circuit device 审中-公开
    半导体集成电路器件

    公开(公告)号：US20040170044A1

    公开(公告)日：2004-09-02

    申请号：US10792094

    申请日：2004-03-04

    Applicant: Renesas Technology Corporation ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Takao Saotome ,  Takeshi Suzuki ,  Hiroyuki Tanaka ,  Shigeru Nakahara ,  Keiichi Higeta

    IPC: G11C005/06

    CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C2029/3202

    Abstract: There is provided a semiconductor integrated circuit device which has realized high speed operation, high integration density and highly efficient layout of the RAM macro, in which a memory array which is divided into four sections in the X and Y coordinates directions is disposed, a first input circuit for receiving a signal which requires optimization for a signal delay is disposed to the center of such four memory arrays, a second input circuit for receiving a data input and control signals thereof is disposed to the center of Y coordinate corresponding to the extending direction of the word line and a signal line for transferring an input signal from the external circuit of the RAM macro to the first and second input circuits is formed using an upper layer wiring for the wiring to form the memory array.

    Abstract translation: 提供了一种半导体集成电路器件，其实现了RAM宏的高速操作，高集成密度和高效布局，其中布置了在X和Y坐标方向上被划分为四个部分的存储器阵列，第一 用于接收需要信号延迟优化的信号的输入电路设置在这样的四个存储器阵列的中心，用于接收数据输入的第二输入电路及其控制信号被设置在对应于延伸方向的Y坐标的中心 并且使用用于布线的上层布线形成用于将来自RAM宏的外部电路的输入信号传送到第一和第二输入电路的信号线，以形成存储器阵列。

    Semiconductor integrated circuit and IC card
    78.
    发明申请
    Semiconductor integrated circuit and IC card 失效
    半导体集成电路和IC卡

    公开(公告)号：US20040151033A1

    公开(公告)日：2004-08-05

    申请号：US10748137

    申请日：2003-12-31

    Applicant: Renesas Technology Corp ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

    IPC: G11C005/00

    CPC classification number: G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

    Abstract: Power wastefully consumed in a memory in standby state is reduced without lowering the speed of operation of reading data out of the memory. A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied. Therefore, the speed of data readout operation is not lowered.

    Abstract translation: 在待机状态的存储器中浪费地消耗的电力降低，而不降低从存储器读出数据的操作速度。 半导体集成电路具有可以进入活动状态或待机状态的存储器，并且存储器具有用于存储单元连接的位线和源极线的电压产生电路。 响应于从活动状态转换到待机状态的指令，电压产生电路使位线的电位和源极线的电位彼此相等。 响应于从待机状态转换到活动状态的指令，电压产生电路产生位线和源极线之间的电位差。 在待机状态下，位线的电位和源极线的电位彼此相等。 因此，每个存储单元的源极和漏极之间不会发生次阈值泄漏。 在活动状态下，源极线电位不变。 因此，数据读出操作的速度不降低。

    Information processing device
    79.
    发明申请
    Information processing device 有权

    公开(公告)号：US20040136530A1

    公开(公告)日：2004-07-15

    申请号：US10745540

    申请日：2003-12-29

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., LTD.

    Inventor： Takashi Endo ,  Masahiro Kaminaga ,  Takashi Watanabe ,  Kunihiko Nakada ,  Takashi Tsukamoto

    IPC: H04L009/00

    CPC classification number: G06F7/501 ,  G06F7/48 ,  G06F21/72 ,  G06F21/755 ,  G06F2207/7219 ,  H04L9/002 ,  H04L9/0861 ,  H04L9/0894

    Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.

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