Abstract:
The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer (114) on top of a native oxide layer above a silicide layer (110) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer (110) and reduce excess silicon consumption. The temperature range can be greater than 350° C. and less than 615° C., but is optimal between 485° C. to 550° C.
Abstract:
Semiconductor structures having dielectric material layers that are below 3 nanometers in thickness can now be measured with greater precision and in less time using a SIMS device. In an example embodiment of the present invention, a method of measuring the thickness of a dielectric material layer of a semiconductor structure formed on a substrate includes directing a high energy ion beam at a portion of the substrate and sputtering off a plurality of targeted ions from the substrate. The thickness of the dielectric material layer is then determined as a function of a dosage level of the targeted ion and a density of the targeted ion in the dielectric material.
Abstract:
A method for the preparation of a sucrose 6-ester comprises:(i) reacting sucrose with a ketene acetal in the presence of an acid catalyst in an inert organic solvent to form a sucrose alkyl 4, 6-orthoester;(ii) subjecting the sucrose alkyl 4, 6-orthoester to mild acidic hydrolysis to provide a mixture of 4- and 6-monoesters of sucrose; and(iii) treating the mixture of sucrose monoesters with a base to convert the sucrose 4-ester into sucrose 6-ester. Sucralose may be prepared by chlorination of sucrose 6-esters prepared according to the invention.