MEASURING DEVICE AND METHOD FOR THE DETECTION OF AN APPROACH TO A HAND -HELD DEVICE
    71.
    发明申请
    MEASURING DEVICE AND METHOD FOR THE DETECTION OF AN APPROACH TO A HAND -HELD DEVICE 审中-公开
    用于检测手持式装置的方法的测量装置和方法

    公开(公告)号:WO2012126992A3

    公开(公告)日:2012-11-15

    申请号:PCT/EP2012055095

    申请日:2012-03-22

    Abstract: The invention relates to a capacitive measuring device for a hand-held device, particularly an electric hand-held device for the detection of an approach to the hand-held device, wherein the capacitive measuring device has a switching device, wherein the ground of the capacitive measuring device is galvanically connectable with an electrically conductive structure of the hand-held device by means of a switching device, and wherein the capacitive measuring device has a ground electrode structure with at least one ground electrode that can be arranged on the hand-held device, wherein the ground of the capacitive hand-held device is galvanically connectable with the at least one ground electrode by means of the switching device. Furthermore, the invention relates to a method for the detection of an approach of a hand to a hand-held device, particularly an electric hand-held device, with a capacitive measuring device according to the invention.

    Abstract translation: 本发明涉及一种用于手持式装置的电容式测量装置,特别是用于检测手持式装置的方法的电动手持式装置,其中电容式测量装置具有开关装置,其中, 电容测量装置通过开关装置与手持式装置的导电结构电连接,并且其中电容测量装置具有接地电极结构,其具有至少一个接地电极,该接地电极可布置在手持式 装置,其中所述电容式手持式装置的接地通过所述开关装置与所述至少一个接地电极电连接。 此外,本发明涉及一种用于通过根据本发明的电容式测量装置检测手到手持式装置,特别是电动手持式装置的方法。

    BUCK SWITCH-MODE POWER CONVERTER LARGE SIGNAL TRANSIENT RESPONSE OPTIMIZER
    72.
    发明申请
    BUCK SWITCH-MODE POWER CONVERTER LARGE SIGNAL TRANSIENT RESPONSE OPTIMIZER 审中-公开
    降压开关模式电源转换器大信号瞬态响应优化器

    公开(公告)号:WO2012012263A3

    公开(公告)日:2012-10-18

    申请号:PCT/US2011044029

    申请日:2011-07-14

    Inventor: DEARBORN SCOTT

    CPC classification number: H02M3/156 H02M2003/1566

    Abstract: A switch mode power supply (SMPS) response to a disturbance is improved by using a hysteretic control in combination with a fixed frequency, pulse-width modulated (PWM) controller for providing robust control and optimizing the response to disturbances in buck or buck derived switch mode power supply (SMPS) system topologies.

    Abstract translation: 开关模式电源(SMPS)对干扰的响应通过结合使用滞后控制和固定频率脉宽调制(PWM)控制器来提高鲁棒控制能力,并优化对降压或降压转换器中干扰的响应 模式电源(SMPS)系统拓扑结构。

    AUTOMATIC FREQUENCY CONTROL UNDER LOW SIGNAL-TO-NOISE CONDITIONS
    73.
    发明申请
    AUTOMATIC FREQUENCY CONTROL UNDER LOW SIGNAL-TO-NOISE CONDITIONS 审中-公开
    低信号噪声条件下的自动频率控制

    公开(公告)号:WO2012088280A3

    公开(公告)日:2012-08-23

    申请号:PCT/US2011066507

    申请日:2011-12-21

    Abstract: A method for determining the carrier frequency offset and the corresponding sample-to- sample phase shift present in the sampled digital signal from the radio of a wireless transceiver is specified. The method divides the CFO range to be covered into a number of intervals and creates, from the received signal, as many parallel derived streams as there are interval endpoints, pre -compensating ("back rotating") the input by the sample-to-sample phase shift corresponding to the particular endpoint. It computes the magnitude and phase values of the correlation of a preamble pattern period with the preamble segment of each derived stream in parallel and uses the largest resulting magnitude value(s) to zoom in on the actual CFO present in the input stream. In order to improve accuracy in the presence of noise and provided there is still input preamble left to work on, it repeats the search for a shorter interval centered on the CFO value located in the first run. The finally located CFO value and the phase value from the corresponding correlation computation then determine the actual CFO and the corresponding sample-to-sample phase shift to be applied for pre- compensation ("back rotation") in an open-loop AFC.

    Abstract translation: 指定用于从无线收发器的无线电装置确定采样的数字信号中存在的载波频率偏移和对应的采样与采样相移的方法。 该方法将要覆盖的CFO范围划分成多个间隔,并从接收到的信号中创建与间隔端点一样多的并行导出流,由采样到目标的输入进行预补偿(“反向旋转”), 对应于特定端点的采样相移。 它并行计算前导码模式周期与每个导出流的前导码段的相关性的幅度和相位值,并使用最大的结果幅度值来放大输入流中存在的实际CFO。 为了提高存在噪声的准确性,只要还有输入前导码可以工作,就重复搜索以位于第一次运行中的CFO值为中心的更短间隔。 最终定位的CFO值和来自相应相关计算的相位值然后确定实际CFO和相应的采样到采样相位在开环AFC中用于预补偿(“反向旋转”)。

    2-PHASE GAIN CALIBRATION AND SCALING SCHEME FOR SWITCHED CAPACITOR SIGMA-DELTA MODULATOR
    74.
    发明申请
    2-PHASE GAIN CALIBRATION AND SCALING SCHEME FOR SWITCHED CAPACITOR SIGMA-DELTA MODULATOR 审中-公开
    开关电容器SIGMA-DELTA调制器的2相增益校准和调整方案

    公开(公告)号:WO2011008928A3

    公开(公告)日:2011-03-10

    申请号:PCT/US2010042096

    申请日:2010-07-15

    CPC classification number: H03M1/0663 H03M1/0665 H03M3/422 H03M3/456 H03M3/464

    Abstract: A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.

    Abstract translation: Σ-Δ调制器可以具有多个电容器对,多个开关,用于将来自多个电容器对的任何一对电容器选择性地耦合到输入信号或参考信号;以及控制单元,用于控制通过开关 以执行两阶段的电荷转移,其中可以选择任何一对电容器分配给输入信号或参考信号,并且其中在多个电荷转移之后,通过循环地旋转电容器对来执行增益误差消除,使得 在旋转周期之后,每个电容器对已经被分配给输入信号的第一预定次数,并且还被分配了第二预定次数到参考信号。

    PROGRAMMABLE INTEGRATED CIRCUIT DEVICE TO SUPPORT INDUCTIVE SENSING
    75.
    发明申请
    PROGRAMMABLE INTEGRATED CIRCUIT DEVICE TO SUPPORT INDUCTIVE SENSING 审中-公开
    可编程集成电路设备支持感应感应

    公开(公告)号:WO2010042361A3

    公开(公告)日:2010-09-02

    申请号:PCT/US2009058979

    申请日:2009-09-30

    CPC classification number: H03K17/96 H03K2217/96038

    Abstract: An integrated circuit device inductive touch analog front end excites selected ones of a plurality of inductive touch sensors and provides analog output signals representative of voltages across the coils of the plurality of inductive touch sensors. Various characteristics of the inductive touch analog front end are programmable, A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. The digital processor may program the characteristics of the inductive touch analog front end. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched).

    Abstract translation: 集成电路器件感应触摸模拟前端激励多个感应触摸传感器中的选定的一个,提供表示多个感应触摸传感器的线圈两端的电压的模拟输出信号。 感应式触摸模拟前端的各种特性是可编程的,A数字处理器控制多个感应式触摸传感器中的每一个的选择,并从感应触摸AFE接收相应的模拟输出电压信号。 数字处理器可以对感应式模拟前端的特性进行编程。 当由数字处理器确定线圈电压的充分变化时,假定该感应式触摸传感器已被致动,并且数字处理器基于多个感应式触摸传感器中的哪一个被触发(触摸)而采取行动。

    LOW DROP OUT (LDO) BYPASS VOLTAGE REGULATOR
    76.
    发明申请
    LOW DROP OUT (LDO) BYPASS VOLTAGE REGULATOR 审中-公开
    低压降(LDO)旁路电压稳压器

    公开(公告)号:WO2010062727A3

    公开(公告)日:2010-07-22

    申请号:PCT/US2009063026

    申请日:2009-11-03

    CPC classification number: G05F1/575

    Abstract: A power element bypass and voltage regulation circuit shutdown is used in a low drop out (LDO) bypass voltage regulator to minimize current drawn by the voltage regulator circuit when the supply input voltage approaches the regulated output voltage of the voltage regulation circuit. Two modes of operation are used in the low drop out (LDO) bypass voltage regulator. A regulate mode is used when the supply input voltage is greater than the reference voltage input, and a track mode is used when the supply input voltage is less than or equal to approximately the regulated output voltage of the voltage regulation circuit. Hysteresis may be introduced when switching between the regulate and track modes of operation.

    Abstract translation: 在低压降(LDO)旁路电压调节器中使用电源元件旁路和电压调节电路关断,以最小化当电源输入电压接近电压调节电路的稳压输出电压时由电压调节器电路汲取的电流。 低压降(LDO)旁路电压调节器采用两种工作模式。 当电源输入电压大于参考电压输入时,使用调节模式,当电源输入电压小于或等于电压调节电路的稳压输出电压时,使用轨迹模式。 在调节和跟踪操作模式之间切换时可能会引入迟滞。

    READ AND WRITE INTERFACE COMMUNICATIONS PROTOCOL FOR DIGITAL-TO-ANALOG SIGNAL CONVERTER WITH NON-VOLATILE MEMORY
    77.
    发明申请
    READ AND WRITE INTERFACE COMMUNICATIONS PROTOCOL FOR DIGITAL-TO-ANALOG SIGNAL CONVERTER WITH NON-VOLATILE MEMORY 审中-公开
    具有非易失性存储器的数字 - 模拟信号转换器的读写接口通信协议

    公开(公告)号:WO2009091806A3

    公开(公告)日:2009-09-24

    申请号:PCT/US2009030960

    申请日:2009-01-14

    CPC classification number: H03M1/66

    Abstract: A mixed signal integrated circuit device, e.g., digital-to-analog converter (DAC), has a serial interface communication protocol that accesses volatile and/or non-volatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered- up. However, unlike conventional DACs, DACs with non- volatile memory may need special interface communication protocols for effective operation of the DAC and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non- volatile memories of the DAC so that the MCU may access the DACs memories (non-volatile and/or volatile memories). The mixed signal integrated circuit device has a user programmable address.

    Abstract translation: 混合信号集成电路器件(例如数模转换器(DAC))具有串行接口通信协议,该协议访问易失性和/或非易失性存储器并且每当混合信号器件加电时允许预编程的输出电压 。 但是,与传统DAC不同,具有非易失性存储器的DAC可能需要特殊的接口通信协议才能有效操作DAC以及系统主控制器单元(MCU)之间的通信。 提供不违反标准串行总线通信协议的接口通信协议用于在DAC的易失性和非易失性存储器之间进行通信,以便MCU可以访问DAC存储器(非易失性和/或易失性存储器)。 混合信号集成电路器件具有用户可编程地址。

    ETHERNET CONTROLLER
    78.
    发明申请
    ETHERNET CONTROLLER 审中-公开
    以太网控制器

    公开(公告)号:WO2009067685A3

    公开(公告)日:2009-07-16

    申请号:PCT/US2008084382

    申请日:2008-11-21

    CPC classification number: H04L49/40 H04L49/351

    Abstract: An Ethernet controller semiconductor chip has a system control unit, a media access control layer coupled with the system control unit, a physical layer coupled with the media access control layer, wherein the physical layer comprises a receiving port and a transmitting port, a switch control unit for providing a control signal for auto media device interface switching, and a plurality of external pins, wherein four pins are coupled with the receiving and transmitting port of the physical layer and one pin is coupled with the switch control unit for providing external access to the control signal for auto media device interface switching.

    Abstract translation: 以太网控制器半导体芯片具有系统控制单元,与系统控制单元耦合的媒体访问控制层,与媒体访问控制层耦合的物理层,其中物理层包括接收端口和发送端口,开关控制 用于提供用于自动媒体设备接口切换的控制信号的单元和多个外部引脚,其中四个引脚与物理层的接收和发送端口耦合,一个引脚与开关控制单元耦合,用于提供外部访问 用于自动媒体设备接口切换的控制信号。

    CONTROLLER WITH INDIRECT ACCESSIBLE MEMORY
    79.
    发明申请
    CONTROLLER WITH INDIRECT ACCESSIBLE MEMORY 审中-公开
    具有间接可访问记忆的控制器

    公开(公告)号:WO2009067665A2

    公开(公告)日:2009-05-28

    申请号:PCT/US2008084350

    申请日:2008-11-21

    CPC classification number: G06F13/1673 G06F13/128

    Abstract: A controller has an interface, a buffer memory, a first set of registers for accessing the buffer memory, a second set of registers independent from the first set of registers for accessing the buffer memory, and a control unit for decoding and executing buffer memory access commands received by the interface to access the buffer memory through either the first or second set of registers.

    Abstract translation: 控制器具有接口,缓冲存储器,用于访问缓冲存储器的第一组寄存器,独立于用于访问缓冲存储器的第一组寄存器的第二寄存器组,以及用于解码和执行缓冲存储器访问的控制单元 接口接收的命令通过第一组或第二组寄存器访问缓冲存储器。

    SYSTEM AND METHOD FOR TESTING SOFTWARE CODE FOR USE ON A TARGET PROCESSOR
    80.
    发明申请
    SYSTEM AND METHOD FOR TESTING SOFTWARE CODE FOR USE ON A TARGET PROCESSOR 审中-公开
    用于测试用于目标处理器的软件代码的系统和方法

    公开(公告)号:WO2008024701A3

    公开(公告)日:2008-07-24

    申请号:PCT/US2007076289

    申请日:2007-08-20

    CPC classification number: G06F11/3652

    Abstract: A system and method for testing software code for use on a target processor are disclosed. A system includes a test processor which includes a core substantially similar in physical design and functionality to the target processor for which the software code is intended to be used and an emulation ring including a logic interface to facilitate emulation of the test processor using at least one emulation methodology.

    Abstract translation: 公开了一种用于测试在目标处理器上使用的软件代码的系统和方法。 一种系统包括测试处理器,该测试处理器包括在物理设计和功能上与目标处理器基本上相似的核心,该目标处理器旨在使用该软件代码;以及仿真环,其包括逻辑接口,以便于使用至少一个 仿真方法。

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