公开(公告)号：US10922015B2

公开(公告)日：2021-02-16

申请号：US16002534

申请日：2018-06-07

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/177

Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.

公开(公告)号：US20210004339A1

公开(公告)日：2021-01-07

申请号：US16933752

申请日：2020-07-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US10855529B2

公开(公告)日：2020-12-01

申请号：US16679796

申请日：2019-11-11

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: H04L12/24 ,  H03K19/1776 ,  H04L29/06 ,  H04L29/08

Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.

公开(公告)号：US10813187B2

公开(公告)日：2020-10-20

申请号：US16446114

申请日：2019-06-19

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Manuel Gaertner ,  Sergio Lecce ,  Giovanni Luca Torrisi

IPC: H05B33/08 ,  H05B45/37 ,  H05B45/10 ,  H05B45/14 ,  B60Q1/14 ,  B60Q11/00 ,  H05B45/48

Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.

公开(公告)号：US20200036080A1

公开(公告)日：2020-01-30

申请号：US16521757

申请日：2019-07-25

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GmbH

Inventor： Petr OUREDNIK ,  Yvon GOURDOU

IPC: H01Q1/22 ,  H01Q1/38 ,  H01Q7/00

Abstract: An antenna includes two planar coils that are mechanically disposed face to face and electrically connected in series. The antenna is mounted to a disposable consumer product (for example, a cartridge for use with an electronic cigarette). The antenna is configured to support near field communications with a reader circuit for purposes of authenticating use of the disposable consumer product.

公开(公告)号：US20190306941A1

公开(公告)日：2019-10-03

申请号：US16446114

申请日：2019-06-19

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Manuel Gaertner ,  Sergio Lecce ,  Giovanni Luca Torrisi

IPC: H05B33/08 ,  B60Q1/14 ,  B60Q11/00

Abstract: An integrated device for driving a lighting load, such as a LED, has a first memory element, configured to store a nominal duty-cycle at a nominal supply voltage. An actual voltage acquisition element is configured to detect an actual supply voltage. A processing unit is coupled to the first memory element and to the actual voltage acquisition element and configured to calculate a voltage compensated duty-cycle. A driver unit is coupled to the processing unit and is configured to be supplied according to the voltage compensated duty-cycle.

公开(公告)号：US20190191536A1

公开(公告)日：2019-06-20

申请号：US16285615

申请日：2019-02-26

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Philippe SIRITO-OLIVIER ,  Giovanni Luca TORRISI ,  Manuel GAERTNER ,  Fritz BURKHARDT

IPC: H05B39/02 ,  H05B33/08 ,  B60Q3/80 ,  B60Q1/00 ,  H05B39/04

CPC classification number: H05B39/02 ,  B60Q1/00 ,  B60Q3/80 ,  H05B33/0806 ,  H05B33/0815 ,  H05B39/047

Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.

公开(公告)号：US10231365B2

公开(公告)日：2019-03-12

申请号：US15982534

申请日：2018-05-17

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Domenico Massimo Porto ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Sergio Lecce

IPC: H01H35/00 ,  H01H35/14 ,  H01H37/00 ,  H01H47/24 ,  H01H47/26 ,  H05K7/20 ,  H01L23/34 ,  H03K17/08

Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

公开(公告)号：US20190007202A1

公开(公告)日：2019-01-03

申请号：US16022110

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  H04L9/14 ,  G06F13/36

Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.

公开(公告)号：US20180330127A1

公开(公告)日：2018-11-15

申请号：US15975460

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F21/64 ,  G06F9/38 ,  G06F12/02

CPC classification number: G06F21/83 ,  G06F9/3816 ,  G06F9/445 ,  G06F12/02 ,  G06F21/57 ,  G06F21/64 ,  G06F21/74 ,  G06F2212/7209 ,  H04L9/3234 ,  H04L63/0853

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.