Digital frequency divider
    71.
    发明申请
    Digital frequency divider 有权
    数字分频器

    公开(公告)号:US20030020522A1

    公开(公告)日:2003-01-30

    申请号:US10099588

    申请日:2002-03-13

    Inventor: Andrew Dellow

    CPC classification number: H03K23/68 H03K21/10 H03K23/66

    Abstract: A digital frequency divider has a single circulating shifter register loaded with a bit sequence of variable length and having two outputs adjacent such that are output is equal to the other delayed by one clock period. The outputs are passed to a multiplexer via further logic, the multiplexer selecting one of two inputs depending on whether a clock is high or low. Program logic is provided so that the circuit is configurable for odd, even or half integer division by detecting changes in the bit sequence between 0 and 1 and selectively nulldeletingnull the first half clock cycle when a change is detected. This allows even, odd or half integer clock division with an nullevennull mark space ratio.

    Abstract translation: 数字分频器具有单个循环移位寄存器,其加载可变长度的位序列,并且具有相邻的两个输出,使得输出等于另一个延迟一个时钟周期。 输出通过另外的逻辑被传送到多路复用器,多路复用器根据时钟是高还是低选择两个输入之一。 提供程序逻辑,使得通过检测0和1之间的位序列的变化,并且当检测到改变时选择性地“删除”前半个时钟周期,电路可配置为奇,偶或半整数除法。 这允许偶数,奇数或半整数时钟分频与“偶数”标记空间比。

    Method for sharing configuration data for high logic density on chip
    72.
    发明申请
    Method for sharing configuration data for high logic density on chip 有权
    用于共享芯片上高逻辑密度的配置数据的方法

    公开(公告)号:US20020194449A1

    公开(公告)日:2002-12-19

    申请号:US10172355

    申请日:2002-06-14

    Inventor: Ankur Bal

    CPC classification number: H03K19/17728

    Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

    Abstract translation: 提供了一种用于减少实现布尔函数所需的查找表中可编程体系结构元素数量或相同或逻辑等价的操作的系统。 该系统可以包括连接到多个解码器的输入的单组存储元件,并且存储元件可以由解码器同时访问以向其提供同时多个输出。

    Solid state image sensors and microlens arrays
    73.
    发明申请
    Solid state image sensors and microlens arrays 有权
    固态图像传感器和微透镜阵列

    公开(公告)号:US20020079491A1

    公开(公告)日:2002-06-27

    申请号:US10008606

    申请日:2001-12-06

    Inventor: Jeff Raynor

    CPC classification number: H01L27/14627

    Abstract: A solid state image sensor includes an array of pixels and a corresponding array of microlenses. The positions of the microlenses relative to their corresponding pixels may vary according to the distances of the pixels from a central optical axis of the image sensor to substantially eliminate vignetting of light collected by the microlenses.

    Abstract translation: 固态图像传感器包括像素阵列和相应的微透镜阵列。 微透镜相对于其对应像素的位置可以根据像素与图像传感器的中心光轴的距离而变化,以基本上消除由微透镜收集的光的渐晕。

    Sharing memory access by multiple controllers having different bus widths
    74.
    发明申请
    Sharing memory access by multiple controllers having different bus widths 有权
    由具有不同总线宽度的多个控制器共享内存访问

    公开(公告)号:US20020010841A1

    公开(公告)日:2002-01-24

    申请号:US09972548

    申请日:2001-10-05

    Inventor: Fabrizio Rovati

    CPC classification number: G06F13/1678

    Abstract: There is disclosed a method and circuit for allowing access to a shared memory by at least two controllers having different bus widths. Such method and circuit provides particular advantages in its application to controlling access to a shared memory in a digital set-top-box of a digital television receiver. An arbiter is provided to access between memory accesses by first and second memory access circuitry. The first memory access circuitry accesses a block of data in the shared memory, and the second memory access circuitry accesses two blocks of data in each memory access. Each second memory write access comprises reading blocks of data from first and second memory locations and then writing blocks of data to first and second memory locations.

    Abstract translation: 公开了一种用于允许具有不同总线宽度的至少两个控制器访问共享存储器的方法和电路。 这种方法和电路在其用于控制​​对数字电视接收机的数字机顶盒中的共享存储器的访问方面提供了特别的优点。 提供仲裁器以访问由第一和第二存储器访问电路进行的存储器访问。 第一存储器访问电路访问共享存储器中的数据块,并且第二存储器访问电路在每个存储器访问中访问两个数据块。 每个第二存储器写访问包括从第一和第二存储器位置读取数据块,然后将数据块写入第一和第二存储器位置。

    NFC charging
    75.
    发明授权

    公开(公告)号:US11943008B2

    公开(公告)日:2024-03-26

    申请号:US18153958

    申请日:2023-01-12

    Abstract: The present disclosure relates to a method for aligning a smartphone providing NFC wireless power for charging a battery of a device, the method comprising: emitting, with a first NFC antenna of the smartphone, an NFC field for wirelessly charging the battery of the device comprising a second NFC antenna; obtaining, with the smartphone, a measured value of a signal representative of the NFC field strength between the smartphone and the device; determining, by the smartphone, a range of values of a plurality of ranges of values the measured value belongs; and emitting, by the smartphone, at least one notification signal to a user with a frequency determined by the determined range of values.

    Discharge of an AC capacitor using totem-pole power factor correction (PFC) circuitry

    公开(公告)号:US11936288B2

    公开(公告)日:2024-03-19

    申请号:US17548754

    申请日:2021-12-13

    CPC classification number: H02M1/4208 H02M7/1557 H02M7/217 H02M1/322

    Abstract: An AC capacitor is coupled to a totem-pole type PFC circuit. In response to detection of a power input disconnection, the PFC circuit is controlled to discharge the AC capacitor. The PFC circuit includes a resistor and a first MOSFET and a second MOSFET coupled in series between DC output nodes with a common node coupled to the AC capacitor. When the disconnection event is detected, one of the first and second MOSFETs is turned on to discharge the AC capacitor with a current flowing through the resistor and the turned on MOSFET. Furthermore, a thyristor may be simultaneously turned on, with the discharge current flowing through a series coupling of the MOSFET, resistor and thyristor. Disconnection is detected by detecting a zero-crossing failure of an AC power input voltage or lack of input voltage decrease or input current increase in response to MOSFET turn on for a DC input.

    CLIFF DETECTION IN ROBOTIC DEVICES
    77.
    发明公开

    公开(公告)号:US20230356397A1

    公开(公告)日:2023-11-09

    申请号:US17661899

    申请日:2022-05-03

    CPC classification number: B25J9/1666 B25J9/163 B25J9/1694

    Abstract: Cliff Detection in Robotic Devices A method of operating a robotic device includes: moving the robotic device towards an edge of a cliff while a ToF sensor senses reflected signals having been transmitted by the ToF sensor, the reflected signals being generated by the signals transmitted by the ToF sensor being reflected off a target object back to the ToF sensor, the ToF sensor being attached to a front of the robotic device and including an array of single-photon avalanche diode (SPAD) sensors; comparing a statistical distribution of the reflected signals received at a plurality of different rows of zones configured by the array of SPADs in a region of interest (ROI) of the ToF sensor and based on the comparing detecting an approaching of the edge of the cliff; and in response to detecting the approaching of the edge, changing a propulsion of the robotic device before reaching the edge.

    SYNCHRONIZATION CIRCUIT FOR OSCILLATING MIRROR AND LASER

    公开(公告)号:US20230070845A1

    公开(公告)日:2023-03-09

    申请号:US17987250

    申请日:2022-11-15

    Inventor: Elik HARAN

    Abstract: A control system includes a mirror controller generating horizontal and vertical mirror synchronization signals for a mirror based upon a mirror clock signal. Laser modulation circuitry generates horizontal and vertical laser synchronization signals as a function of first and second laser clock signals and generates control signals for a laser that emits a laser beam that impinges on the mirror. First synchronization circuitry receives the horizontal mirror synchronization signal and the horizontal laser synchronization signal, and modifies generation of the first laser clock signal to achieve alignment between the horizontal mirror synchronization signal and horizontal laser synchronization signal. Second synchronization circuitry receives the vertical mirror synchronization signal and the vertical laser synchronization signal, and modifies generation of the second laser clock signal to achieve alignment between the vertical mirror synchronization signal and vertical laser synchronization signal.

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