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公开(公告)号：KR1019960009995B1
公开(公告)日：1996-07-25
申请号：KR1019920013817
申请日：1992-07-31
Applicant: 삼성전자주식회사
IPC: H01L27/10
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11541 , H01L27/11543
Abstract: a storage cell which comprises a floating gate electrode (204) formed on a tunnel oxide layer (203), a polycrystalline silicon thin film (206) formed on an interface insulating layer (205) and a control gate electrode (208) formed on a polycrystalline silicon thin film (206); a transistor comprising the floating gate electrode (204) formed on a gate oxide (202), the interface insulating layer (205) and the polycrystalline silicon thin film (206) formed on the floating gate electrode (204) and the control gate electrode (208) connected to a floating gate electrode at one point and formed on the polycrystalline silicon thin film (206).
Abstract translation: 存储单元，其包括形成在隧道氧化物层（203）上的浮栅电极（204），形成在界面绝缘层（205）上的多晶硅薄膜（206）和形成在栅极电极 多晶硅薄膜（206）; 形成在栅极氧化物（202）上的浮栅电极（204），形成在浮栅电极（204）和控制栅极电极（204）上的界面绝缘层（205）和多晶硅薄膜（206） 208），其一端连接到浮栅，并形成在多晶硅薄膜（206）上。
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公开(公告)号：KR1019960000616B1
公开(公告)日：1996-01-10
申请号：KR1019930000390
申请日：1993-01-13
Applicant: 삼성전자주식회사
IPC: G11C16/00
Abstract: The device consists of a number of word line formed on a semiconductor substrate, a number of cell unit array which has more than one memory transistor with a source and drain regions, a floating gate formed on the channel region between the source and the drain regions, a control gate on the floating gate which is connected to the word line, a memory block which is composed of a number of cell unit, and an unit which floats the word line connected to the memory transistor of the memory block that are unselected by an address and performs the capacitive coupling of the most of eliminating voltage.
Abstract translation: 该器件由形成在半导体衬底上的多个字线组成，多个单元阵列阵列具有多个具有源区和漏极区的存储晶体管，形成在源区和漏区之间的沟道区上的浮置栅 ，连接到字线的浮动栅极上的控制栅极，由多个单元单元组成的存储块，以及浮动连接到存储器块的存储晶体管的字线的单元，该单元未被选择的单元 一个地址并执行大部分消除电压的电容耦合。
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公开(公告)号：KR1019950034270A
公开(公告)日：1995-12-28
申请号：KR1019940009986
申请日：1994-05-07
Applicant: 삼성전자주식회사
Inventor： 최정혁
IPC: G11C16/06
Abstract: 본 발명은 반도체 메모리장치에 관한 것으로, 반도체 기판상의 채널영역과 터널산화막으로 이격되는 플로팅 게이트 및 상기 플로팅게이트와 중간 절연막을 개재하여 대응 워드라인에 접속되는 제어게이트를 구비하는 다수 개의 메모리 트랜지스터가 소오스-드레인영역에 의해 채널이 서로 직렬접속된 낸드셀 스트링과, 상기 낸드셀 스트링의 일단을 대응 비트라인에 접속하는 제1선택수단을 구비하는 전기적으로서 소거 및 프로그램 가능한 독출 전용 메모리장치에 있어서, 상기 제1선택수단과 비트 라인사이에 접속되는 미리설정된 저항값을 가지는 저항소자와, 상기 낸드셀 스트링을 통하여 흐르는 전류에 따라 상기 비트라인에 공급되는 전류의 방전경로를 증폭하는 증폭소자를 더 구비하는 독출전용 메모리 장치를 제공한다.
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公开(公告)号：KR100084862B1
公开(公告)日：1995-05-17
申请号：KR1019910024488
申请日：1991-12-26
Applicant: 삼성전자주식회사
Inventor： 최정혁
IPC: H01L27/115
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公开(公告)号：KR1019940011811B1
公开(公告)日：1994-12-26
申请号：KR1019910024666
申请日：1991-12-27
Applicant: 삼성전자주식회사
Inventor： 최정혁
IPC: H01L27/10
Abstract: The method includes the steps of forming a tunnel oxide film (2) on the substrate (1) to deposit a 1st conducting layer (3) to form a floating gate pattern, forming an interlayered insulating layer (4) and a 2nd conducting layer (5) thereon to etch the layers (5,4,3) to form a memory cell, depositing insulating layers (7,8,9) thereon to etch-back the layer (9) to form a spacer (9') on the side wall of the cell to etch the exposed layer (8), implanting P type impurities to remove the spacer to form a mini field oxide film (11), and implanting n-type impurities to form a source region to deposit and etch-back a 3rd conducting layer (12) thereon to form a source line (12).
Abstract translation: 该方法包括以下步骤：在衬底（1）上形成隧道氧化膜（2）以沉积第一导电层（3）以形成浮栅图案，形成层间绝缘层（4）和第二导电层 5）以蚀刻层（5,4,3）以形成存储单元，在其上沉积绝缘层（7,8,9）以蚀刻所述层（9）以在其上形成间隔物（9'） 蚀刻暴露层（8），注入P型杂质以移除间隔物以形成微型氧化膜（11），并注入n型杂质以形成源区以沉积和回蚀 在其上形成第三导电层（12）以形成源极线（12）。
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Patent Agency Ranking
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公开(公告)号：KR1019940009645B1
公开(公告)日：1994-10-15
申请号：KR1019910020706
申请日：1991-11-20
Applicant: 삼성전자주식회사
IPC: H01L27/10
Abstract: A method includes the steps of forming a first conductive layer on a semiconductor substrate on which a field oxide layer, a gate oxide layer and a tunnel oxide layer are formed, sequentially forming an interlevel insulating layer, a second conductive layer and a first insulating layer on the first conductive layer, selectively etching the first insulating layer, forming a second insulating layer on the resultant, selectively exposing the second insulating layer, removing the second insulating layer, removing the exposed second conductive layer, the interlevel insulating layer and the first conductive layer, selectively etching the first insulating layer, second conductive layer, interlevel insulating layer and first conductive layer, forming a diffusion region on a predetermined portion of the substrate, forming a planarizing layer on the overall surface of the substrate, forming a contact hole through photolithography, and forming a metal layer on a predetermined portion.
Abstract translation: 一种方法包括以下步骤：在半导体衬底上形成第一导电层，其上形成有场氧化物层，栅氧化层和隧道氧化物层，依次形成层间绝缘层，第二导电层和第一绝缘层 在第一导电层上，选择性地蚀刻第一绝缘层，在所得第一绝缘层上形成第二绝缘层，选择性地暴露第二绝缘层，去除第二绝缘层，去除暴露的第二导电层，层间绝缘层和第一导电层 选择性地蚀刻第一绝缘层，第二导电层，层间绝缘层和第一导电层，在基板的预定部分上形成扩散区域，在基板的整个表面上形成平坦化层，形成接触孔 并且在预定部分上形成金属层。
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公开(公告)号：KR1019920013707A
公开(公告)日：1992-07-29
申请号：KR1019900020261
申请日：1990-12-10
Applicant: 삼성전자주식회사
Inventor： 최정혁
IPC: H01L27/10 , H01L27/112
Abstract: 내용 없음
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