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公开(公告)号：KR1020140008098A
公开(公告)日：2014-01-21
申请号：KR1020120075172
申请日：2012-07-10
Applicant: 삼성전자주식회사
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483
Abstract: The present invention relates to a reading method of a memory device including a memory cell including a first or N program state and a removing state comprising: a step of determining first reading power of the first program state and the removing state based on the distribution change of the first program state and the distribution change of the removing state; and a step of determining the other reading power among the second or the N reading power based on the one reading power by determining the one reading power among the second or the N reading power based on the distribution change of two program states among the first or the N program state. N is bigger than 3 and is a natural number. [Reference numerals] (S310) Determining first read voltage based on the distribution change of a first program state and a removal state; (S320) Determining second or N read voltage based on one or more distribution changes among first or N program states
Abstract translation: 本发明涉及一种存储装置的读取方法，该存储装置包括具有第一或第N编程状态和去除状态的存储单元，包括：基于分布变化确定第一编程状态的第一读取功率和去除状态的步骤 的第一程序状态和去除状态的分布变化; 以及基于所述一个读取功率，通过基于所述第二或所述N个读取功率中的所述第二或所述N个读取功率中的两个编程状态的分布改变来确定所述第二或所述N个读取功率中的所述另一个读取功率的步骤， N程序状态。 N大于3，是自然数。 （参考号）（S310）基于第一编程状态和去除状态的分布变化来确定第一读取电压; （S320）基于第一或N个编程状态中的一个或多个分布变化确定第二或N个读取电压
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公开(公告)号：KR1020130060795A
公开(公告)日：2013-06-10
申请号：KR1020110127049
申请日：2011-11-30
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5621 , G11C16/0483 , G11C16/3427
Abstract: PURPOSE: A non-volatile memory device and an operating method thereof are provided to increase the reliability of data by performing a high speed randomization operation from the inside. CONSTITUTION: A cell array(110) includes a main region(114) and a buffer region(112). The buffer region temporarily stores a plurality of pages to be stored in the main region. A page buffer(130) performs a writing operation or a reading operation of data for the main region and the buffer region. An on-chip randomizer(140) randomizes the data stored in the page buffer based on an address provided from the outside.
Abstract translation: 目的：提供一种非易失性存储器件及其操作方法，以通过从内部执行高速随机化操作来提高数据的可靠性。 构成：单元阵列（110）包括主区域（114）和缓冲区域（112）。 缓冲区域临时存储要存储在主区域中的多个页面。 页面缓冲器（130）对主区域和缓冲区域执行写入操作或数据的读取操作。 片上随机化器（140）基于从外部提供的地址随机化存储在页缓冲器中的数据。
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公开(公告)号：KR1020130049331A
公开(公告)日：2013-05-14
申请号：KR1020110114281
申请日：2011-11-04
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1048 , G06F3/0649 , G06F11/1068 , G06F11/14 , G06F11/1402 , G06F12/0246 , G06F2212/72 , G06F2212/7205 , G11C29/42 , G11C2211/5641 , H03M13/05 , H03M13/3715
Abstract: PURPOSE: A memory system and a data storing method thereof are provided to improve the performance of the memory system by selectively omitting an error detection operation and an error correction operation of data read through an SLC reading operation. CONSTITUTION: A memory system includes a nonvolatile memory device(3100) and a memory controller(3200). The nonvolatile memory device includes a memory cell array to store data. The memory controller controls the nonvolatile memory device. When the data is transmitted from a first memory block to a second memory block of the memory cell array, the memory controller selectively corrects the data read from the first memory block based on one state of the first memory block and the second memory block.
Abstract translation: 目的：提供存储器系统及其数据存储方法，通过选择性地省略通过SLC读取操作读取的数据的错误检测操作和纠错操作来提高存储器系统的性能。 构成：存储器系统包括非易失性存储器件（3100）和存储器控制器（3200）。 非易失性存储器件包括用于存储数据的存储单元阵列。 存储器控制器控制非易失性存储器件。 当数据从第一存储块发送到存储单元阵列的第二存储块时，存储器控制器基于第一存储块和第二存储块的一个状态选择性地校正从第一存储器块读取的数据。
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公开(公告)号：KR1020130011033A
公开(公告)日：2013-01-30
申请号：KR1020110071907
申请日：2011-07-20
Applicant: 삼성전자주식회사
Inventor： 정재용
CPC classification number: G11C16/28 , G11C16/0483 , G11C16/20
Abstract: PURPOSE: A memory system including a nonvolatile memory and a controlling method thereof are provided to secure the reliability of set data stored in a latch unit by sensing the sensed set data according to the change of reference data again. CONSTITUTION: A nonvolatile memory(100) includes a memory cell array, a first latch unit(141), and a second latch unit(142). A memory cell array stores set data and reference data. The first and second latch units store the reference data and the set data sensed from the memory cell array in a power-up operation, respectively. A controller(200) controls the sensing operation of the nonvolatile memory. The operation environment of the nonvolatile memory is determined according to the set data stored in the first latch unit.
Abstract translation: 目的：提供一种包括非易失性存储器及其控制方法的存储器系统，用于通过再次根据参考数据的变化感测感测到的设定数据来确保存储在锁存单元中的设置数据的可靠性。 构成：非易失性存储器（100）包括存储单元阵列，第一锁存单元（141）和第二锁存单元（142）。 存储单元阵列存储设置数据和参考数据。 第一和第二锁存单元分别在上电操作中存储从存储单元阵列感测的参考数据和设置数据。 控制器（200）控制非易失性存储器的感测操作。 根据存储在第一锁存单元中的设定数据来确定非易失性存储器的操作环境。
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公开(公告)号：KR1020120079875A
公开(公告)日：2012-07-16
申请号：KR1020110001200
申请日：2011-01-06
Applicant: 삼성전자주식회사
Inventor： 정재용
CPC classification number: H04W36/0066 , H04W36/0072 , H04W88/16 , H04W92/20 , H04W16/32 , H04W36/08
Abstract: PURPOSE: A method and apparatus for X2 interface between base stations using gateway in a wireless communication system having hierarchical cell structure is provided to offer X2 interfaces about a plurality of other base stations to each base station. CONSTITUTION: A pico gateway receives a message which requests IP information of a target BS(Base Station) from a source BS(401). The pico gateway obtains the IP information of the target BS(407). The pico gateway maps the source BS with the target BS(409). The pico gateway transmits the IP information of the gateway instead of the target BS IP to the source BS(411).
Abstract translation: 目的：提供一种在具有分层小区结构的无线通信系统中使用网关的基站之间的X2接口的方法和装置，以向每个基站提供关于多个其他基站的X2接口。 构成：微微网关接收从源BS（401）请求目标BS（基站）的IP信息的消息。 微微网关获取目标BS的IP信息（407）。 微微网关将源BS与目标BS（409）进行映射。 微微网关将网关的IP信息而不是目标BS IP发送到源BS（411）。
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Patent Agency Ranking
公开(公告)号：KR1020100073085A
公开(公告)日：2010-07-01
申请号：KR1020080131671
申请日：2008-12-22
Applicant: 삼성전자주식회사
Inventor： 정재용
CPC classification number: G06F17/30893 , G06F9/453 , G06F21/44 , G06F21/50
Abstract: PURPOSE: A method and a device of abstracting device driver for hardware devices in a multi core platform are provided to minimize the change of a device even if an application, operating system, or hardware platform is changed, thereby maximizing reusability of the device driver. CONSTITUTION: A DAC(Device Abstraction Component) execution environment unit(126) provides execution environment of device abstraction component(124). A physical input/output interface unit(122) provides interface for access of hardware device. To independently execute the DAC(Device Abstraction Component) with operating system(130) or application software(140), a DAC-RTM(Run-Time Module) performs providing additional function necessary for executing the mapping of the interface and the DAC.
Abstract translation: 目的：提供一种在多核平台中为硬件设备抽象设备驱动程序的方法和设备，以便即使应用程序，操作系统或硬件平台发生变化，也可最大限度地减少设备的变化，从而最大化设备驱动程序的可重用性。 构成：DAC（设备抽象组件）执行环境单元（126）提供设备抽象组件（124）的执行环境。 物理输入/输出接口单元（122）提供用于访问硬件设备的接口。 为了使用操作系统（130）或应用软件（140）独立地执行DAC（设备抽象组件），DAC-RTM（运行时模块）执行提供执行接口和DAC的映射所需的附加功能。
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公开(公告)号：KR1020100053201A
公开(公告)日：2010-05-20
申请号：KR1020080112217
申请日：2008-11-12
Applicant: 삼성전자주식회사
CPC classification number: G11C16/16 , G11C16/344 , G11C16/3445
Abstract: PURPOSE: An erasing method of a flash memory is provided to reduce time for erasing a flash memory cell by selectively programming a flash memory cell with a voltage level which is less than a critical voltage. CONSTITUTION: At least one flash memory cell is eliminated based on a first erase voltage(S120). A flash memory cell with a critical voltage less than the first voltage is detected among at least one flash memory cell(S140). A critical voltage of a flash memory cell detected among at least one flash memory cell is changed to a second voltage with a voltage level more than the first voltage(S160). At least one flash memory cell is verified based on the first test voltage(S180).
Abstract translation: 目的：提供闪速存储器的擦除方法，以通过以小于临界电压的电压电平选择性地编程闪存单元来减少擦除闪存单元的时间。 构成：基于第一擦除电压消除至少一个闪存单元（S120）。 在至少一个闪存单元中检测具有小于第一电压的临界电压的闪存单元（S140）。 在至少一个闪存单元中检测到的闪存单元的临界电压被改变为具有大于第一电压的电压电平的第二电压（S160）。 基于第一测试电压验证至少一个闪存单元（S180）。
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公开(公告)号：KR100946886B1
公开(公告)日：2010-03-09
申请号：KR1020060011678
申请日：2006-02-07
Applicant: 삼성전자주식회사
Abstract: 본 발명은 무선 이동 통신 시스템에서, 이동국의 초기 네트워크 진입 방법에 있어서, 상기 이동국의 제품군 식별자 주소를 포함하는 매체 접속 제어(MAC) 주소가 포함된 레인징 요구 메시지를 기지국으로 송신하는 과정과, 상기 기지국으로부터 상기 제품군 식별자 주소에 대응하는 기본 용량 협상 및 등록 절차와 관련된 정보가 포함된 레인징 응답 메시지를 수신하는 과정을 포함한다.
초기 레인징, 네트워크 진입, 인증, 기본 용량 협상-
公开(公告)号：KR100888847B1
公开(公告)日：2009-03-17
申请号：KR1020070064556
申请日：2007-06-28
Applicant: 삼성전자주식회사
CPC classification number: G11C11/5628 , G11C16/3454 , G11C2211/5621
Abstract: 본 발명은 불휘발성 반도체 메모리 장치 및 그것의 프로그램 방법에 관한 발명이다. 본 발명에 따른 프로그램 방법은 메모리 셀에 대한 제 1 프로그램 동작을 수행하고, 상기 제 1 프로그램 동작 완료 후에 회복 읽기 동작을 수행하여 원 데이터를 회복하고, 상기 제 1 프로그램 동작시 사용되는 검증 읽기 전압보다 높은 레벨의 검증 읽기 전압을 사용하여 상기 메모리 셀에 대한 제 2 프로그램 동작을 수행한다.
Abstract translation: 本发明涉及一种非易失性半导体存储器件及其编程方法。 根据本发明的编程方法在存储单元上执行第一编程操作，在完成第一编程操作之后执行恢复读操作以恢复原始数据， 并且使用高电平验证读取电压对存储器单元执行第二编程操作。
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公开(公告)号：KR1020090020928A
公开(公告)日：2009-02-27
申请号：KR1020070085572
申请日：2007-08-24
Applicant: 삼성전자주식회사
CPC classification number: G06F12/0246 , G06F2212/7202 , G11C11/5628 , G11C16/10 , G11C2216/14
Abstract: A semiconductor memory device capable of programming simultaneously a plurality of banks and a method thereof are provided to improve a programming speed of a NOR flash memory device by programming simultaneously a plurality of banks by using data buffers corresponding to all or a part of the banks. A semiconductor memory device includes a memory cell array(120) and a plurality of data buffers(140-1~140-i). The memory cell array includes a plurality of banks(120-1~120-i). The data buffers are formed to store program data to be programmed in the banks.
Abstract translation: 提供了能够同时编程多个存储体的半导体存储器件及其方法，用于通过使用与所有或一部分存储体相对应的数据缓冲器同时编程多个存储体来提高NOR闪存器件的编程速度。 半导体存储器件包括存储单元阵列（120）和多个数据缓冲器（140-1〜140-i）。 存储单元阵列包括多个存储体（120-1〜120-i）。 形成数据缓冲器以存储要在存储体中编程的程序数据。
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