公开(公告)号：KR100546777B1

公开(公告)日：2006-01-25

申请号：KR1020030091885

申请日：2003-12-16

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김무섭 ,  강주성 ,  홍도원

IPC: H04L9/06

Abstract: 한국 표준 암호 알고리즘(SEED) 암호화/복호화 장치에 관한 것으로서 특히, 파이프라인 기법과 병렬 프로세싱 기법을 사용하여 고속 처리를 가능하게 한 SEED 암/복호화 장치, 암/복호화 방법, 라운드 처리 방법, 이에 적합한 F함수 처리기에 관한 것이다.
본 발명에 따른 SEED 암/복호화 장치는 외부 프로세서와의 인터페이스를 위한 인터페이스 처리부; 암/복호 블록들의 저장을 위한 데이터 메모리; 병렬로 각각의 암/복호 블록들을 처리하는 제1 및 제2의 SEED 코어들; 상기 제1 및 제2 SEED 코어들에서 필요한 라운드별 키 값들을 생성하는 키 스케줄러; 및 SEED 암/복호 동작에 필요한 동작 모드, 초기값 등을 저장하며, 상기 제1 및 제2 SEED 코어들과 데이터 메모리, 키 스케줄러를 제어하기 위한 SEED 제어기를 포함하는 것을 특징으로 한다.
SEED 암/복호화 장치는 SEED 암호 연산을 지원하지 않는 상용 보안 프로세서들과 PCI 인터페이스를 통하여 연동하게 함으로써 전체 보안 시스템의 처리 성능을 향상시킬 수 있다는 효과를 가진다.

公开(公告)号：KR1020050054776A

公开(公告)日：2005-06-10

申请号：KR1020030088411

申请日：2003-12-06

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  최용제 ,  강주성 ,  정교일

IPC: G06K19/073

Abstract: 본 발명에 의한 비접촉 IC 카드의 전자기장 분석 공격 방지 장치 및 그 방법은 외부에서 유입되는 RF신호에서 전원을 유도하는 전원공급부; 상기 유도된 전원으로부터 전하를 축적하여 내부에 전류를 공급하는 제1전하축적부; 상기 유도된 전원으로부터 전하를 축적하며 상기 내부에 공급되는 전류가 소정의 기준치 이하일 경우 발생하는 제어신호에 의하여 상기 제1전하축적부와 함께 소요되는 전류를 공급하는 제2전하축적부; 및 상기 제1전하축적부의 전하변화량을 감시하면서 상기 내부에 공급되는 전류의 감소가 감지되면 상기 제어신호를 발생하는 제어부;를 포함하는 것을 특징으로 하며, 비접촉 IC카드 시스템의 내부회로의 전반적인 재설계나 연산의 성능을 저하시키는 연산 알고리즘의 변화없이, 전자기장 분석공격 방지회로를 사용하여 비접촉 IC카드 시스템에 가해지는 전자기장 분석공격을 방지함으로써, 효율적인 카드 시스템의 보안성 향상을 가져올 수 있으며, RF신호를 이용하는 다른 시스템들에 적용되어 사용 되어질 수 있다.

公开(公告)号：KR100453230B1

公开(公告)日：2004-10-15

申请号：KR1020020069061

申请日：2002-11-08

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  최용제 ,  김무섭 ,  류희수

IPC: H04L9/16

CPC classification number: G06F7/725

Abstract: In an apparatus for a hyperelliptic-curve cryptography processing, an input/output control block controls a peripheral component interconnect (PCI) interface block, a direct memory access (DMA) and a data input/output. An input memory block stores an external instruction and input data provided by the PCI interface block. An output memory block stores a final and an intermediate value of a hyperelliptic-curve cryptography operation. A MUX controls a path of input/output data. An operation core block performs a genus one elliptic-curve and a genus two hyperelliptic-curve cryptography algorithm, respectively. A controlling device controls the operation core block.

Abstract translation: 在用于超椭圆曲线密码处理的设备中，输入/输出控制块控制外围组件互连（PCI）接口块，直接存储器访问（DMA）和数据输入/输出。 输入存储器块存储由PCI接口模块提供的外部指令和输入数据。 输出存储器块存储超椭圆曲线密码术操作的最终值和中间值。 MUX控制输入/输出数据的路径。 运算核心块分别执行属于一个椭圆曲线和属于两个超椭圆曲线密码算法。 控制设备控制运行核心块。

公开(公告)号：KR1020040055523A

公开(公告)日：2004-06-26

申请号：KR1020020082218

申请日：2002-12-21

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  정교일

IPC: G06F7/52

Abstract: PURPOSE: A device for operating the finite field multiplication of GF(p) and GF(2¬m) is provided to perform all of a GF(p) and a GF(2¬m) elliptic curve cryptosystem by performing a GF(p) decimal finite field multiplication operation and a GF(2¬m) binary finite field multiplication operation. CONSTITUTION: An Nx1 multiplier(400) performs the bit multiplication of a multiplier and a multiplicand. An upper CLA(Carry-Look-Ahead) adder(800) adds the output of the Nx1 multiplier, a sum storing register(1100), and a carry storing register(1200). A lower CLA adder(1000) adds or subtracts two sums of the upper CLA adder, the carry output, and a modular value. A negative number converter(600) converts the modular value into a negative number. For the GF(p) finite field operation, a CSA(Carry-Select-Adder)(1600) adds/outputs the final sum provided from the sum storing register and the carry provided from the carry storing register. A carry register(1500) stores the carry information of the CSA adder. A controller(700) controls each register and input selector for the multiplication operation of each finite field.

Abstract translation: 目的：提供用于操作GF（p）和GF（2-m）的有限域乘法的装置，以通过执行GF（p）和GF（2）来执行所有GF（p）和GF（2-m）椭圆曲线密码系统 ）十进制有限域乘法运算和GF（2-m）二进制有限域乘法运算。 构成：Nx1乘法器（400）执行乘法器和被乘数的乘法运算。 上层CLA（进位前进）加法器（800）将N×1乘法器的输出，和存储寄存器（1100）和进位存储寄存器（1200）相加。 较低的CLA加法器（1000）加上或减去上CLA加法器，进位输出和模数值的两个和。 负数转换器（600）将模块值转换为负数。 对于GF（p）有限域操作，CSA（进位选择加法器）（1600）从和存储寄存器提供的最终和从进位存储寄存器提供的进位相加/输出。 进位寄存器（1500）存储CSA加法器的进位信息。 控制器（700）控制每个有限域的乘法运算的每个寄存器和输入选择器。

公开(公告)号：KR1020040041186A

公开(公告)日：2004-05-17

申请号：KR1020020069061

申请日：2002-11-08

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  최용제 ,  김무섭 ,  류희수

IPC: H04L9/16

CPC classification number: G06F7/725

Abstract: PURPOSE: A hyperelliptic curve encryption processing system is provided to process a hyperelliptic curve encryption algorithm within a short period of time by performing simultaneously a hyperelliptic curve encryption algorithm having a genus parameter of 1 and the hyperelliptic curve encryption algorithm having the genus parameter of 2. CONSTITUTION: A hyperelliptic curve encryption processing system includes an input/output control block(120), an input memory block(140), an output memory block(150), a MUX(160), an encryption core block(180), and a control unit(170). The input/output control block(120) controls an operation of a PCI interface block, a DMA(Direct Memory Access) operation, and a data input/output operation. The input memory block(140) stores external commands and input data from the PCI interface block. The output memory block(150) stores a result value and an intermediate value of a hyperelliptic curve encryption calculation process. The MUX(160) controls an input/output data path of an input memory block and an output memory block. The encryption core block(180) performs a hyperelliptic curve encryption algorithm having a genus parameter of 1 and the hyperelliptic curve encryption algorithm having the genus parameter of 2 according to the external commands and the input data of the MUX. The control unit(170) controls the encryption core block according to a command of the input memory block.

Abstract translation: 目的：提供超椭圆曲线加密处理系统，通过同时执行属性参数为1的超椭圆曲线加密算法和属性参数为2的超椭圆曲线加密算法，在短时间内处理超椭圆曲线加密算法。 构成：超椭圆曲线加密处理系统包括输入/​​输出控制块（120），输入存储块（140），输出存储块（150），MUX（160），加密核心块（180）和 控制单元（170）。 输入/输出控制块（120）控制PCI接口块的操作，DMA（直接存储器访问）操作和数据输入/输出操作。 输入存储器块（140）存储来自PCI接口块的外部命令和输入数据。 输出存储器块（150）存储结果值和超椭圆曲线加密计算处理的中间值。 MUX（160）控制输入存储块和输出存储块的输入/输出数据路径。 加密核心块（180）根据外部命令和MUX的输入数据执行属性参数为1的超椭圆曲线加密算法，具有属性参数为2的超椭圆曲线加密算法。 控制单元（170）根据输入存储块的命令控制加密核心块。

公开(公告)号：KR100406139B1

公开(公告)日：2003-11-14

申请号：KR1020010074634

申请日：2001-11-28

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  김무섭 ,  최용제 ,  박영수 ,  정교일

IPC: H04L9/14

Abstract: PURPOSE: A symmetric and asymmetric key cryptography operation process system and a processing method thereof are provided to process various kinds of ciphering algorithm by using the cryptographic operation process system including hardware circuits of small number. CONSTITUTION: A command extraction portion(130) extracts a command for performing a cryptographic operation when commands and data for a ciphering algorithm are received from an external network. A scheduler and decoder portion(120) decides a calculation method and schedules an executing order by analyzing an input command according to the extracted command and the data. A storage portion(140) stores the extracted command and the data received from the external network. A cryptographic operation portion(160) processes a symmetric and an asymmetric cryptographic operation by performing the stored command according to the scheduled executing order. A control portion(150) controls the cryptographic operation portion.

Abstract translation: 目的：提供一种对称和非对称密钥密码操作处理系统及其处理方法，以通过使用包括少数的硬件电路的密码操作处理系统处理各种加密算法。 构成：当从外部网络接收到用于加密算法的命令和数据时，命令提取部分（130）提取用于执行密码操作的命令。 调度器和解码器部分（120）根据提取的命令和数据通过分析输入命令来决定计算方法并调度执行顺序。 存储部分（140）存储提取的命令和从外部网络接收的数据。 密码操作部分（160）通过根据所安排的执行次序执行所存储的命令来处理对称密码操作和非对称密码操作。 控制部分（150）控制密码操作部分。

公开(公告)号：KR1020030051992A

公开(公告)日：2003-06-26

申请号：KR1020010081717

申请日：2001-12-20

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  김호원 ,  최용제 ,  박영수 ,  정교일

IPC: G06F7/552

CPC classification number: G06F21/72 ,  G06F7/72 ,  G06F7/728

Abstract: PURPOSE: An operator RSA(Rivest-Shamir-Adelman) encryption of an IC card is provided to selectively carry out a modular multiplication operation or a modular exponent multiplication operation according to a control signal, and to realize a high speed encryption operation through the minimal access to a memory by storing a middle value in an internal register instead of the memory. CONSTITUTION: An interface(120) transmits/receives the control signal and the encryption operation transmitted from a processor of an IC card system. A control register(130) stores the information for controlling an operation mode according to the control signal. An input register(140) previously reads and stores the data from the memory(110) according to the information stored in the control register(130). A modular part(160) carries out the modular operation and the modular exponent operation by reading the value stored in the input register(140). A controller(140) stores the control signal from the IC card processor in the control register(130), and generates the control signal by offering the data from the memory(110) to the modular part(160).

Abstract translation: 目的：提供IC卡的操作员RSA（Rivest-Shamir-Adelman）加密，以根据控制信号有选择地执行模乘法或模数乘法运算，并通过最小化实现高速加密操作 通过在内部寄存器中存储中间值而不是存储器来访问存储器。 构成：接口（120）发送/接收从IC卡系统的处理器发送的控制信号和加密操作。 控制寄存器（130）根据控制信号存储用于控制操作模式的信息。 输入寄存器（140）根据存储在控制寄存器（130）中的信息，先前从存储器（110）读取并存储数据。 模块化部件（160）通过读取存储在输入寄存器（140）中的值来执行模数运算和模数运算。 控制器（140）将来自IC卡处理器的控制信号存储在控制寄存器（130）中，并通过将数据从存储器（110）提供给模块化部件（160）来产生控制信号。

公开(公告)号：KR1020030043448A

公开(公告)日：2003-06-02

申请号：KR1020010074631

申请日：2001-11-28

Applicant: 한국전자통신연구원

Inventor： 최용제 ,  김호원 ,  김무섭 ,  박영수

IPC: H04L9/14

CPC classification number: H04L9/3093

Abstract: PURPOSE: An NTRU encoding/decoding device is provided to perform efficiently an NTRU encoding/decoding process by improving a structure of the NTRU encoding/decoding device. CONSTITUTION: The first storage portion(12) stores an input message for NTRU encoding and a secret key for NTRU decoding. The second storage portion(13) stores an input value of a polynomial expression using p as a modular value of a coefficient. The third storage portion(14) stores an input value of a polynomial expression using q as a modular value of a coefficient. An NTRU calculation portion(16) performs an NTRU cryptographic calculation and a decoding calculation for values of the first to the third storage portions. The fourth storage portion(17) stores an output value of the NTRU calculation portion. An output selection portion(18) determines an output operation of the fourth storage portion. A modular calculation portion(19) performs a modular calculation process for an output value of the output selection portion. An NTRU control portion(15) controls each register and the NTRU calculation portion.

Abstract translation: 目的：提供NTRU编码/解码装置，通过改进NTRU编码/解码装置的结构来有效地执行NTRU编码/解码处理。 构成：第一存储部分（12）存储用于NTRU编码的输入消息和用于NTRU解码的秘密密钥。 第二存储部（13）使用p作为系数的模块值来存储多项式表达式的输入值。 第三存储部分（14）使用q作为系数的模块值来存储多项式表达式的输入值。 NTRU计算部分（16）对第一至第三存储部分的值执行NTRU密码计算和解码计算。 第四存储部（17）存储NTRU计算部的输出值。 输出选择部分（18）确定第四存储部分的输出操作。 模块化计算部分（19）对输出选择部分的输出值执行模块化计算处理。 NTRU控制部分（15）控制每个寄存器和NTRU计算部分。

公开(公告)号：KR1020030043447A

公开(公告)日：2003-06-02

申请号：KR1020010074630

申请日：2001-11-28

Applicant: 한국전자통신연구원

Inventor： 김호원 ,  김무섭 ,  최용제 ,  박영수 ,  정교일

IPC: H04L9/14

CPC classification number: H04L63/0485 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/302 ,  H04L9/3066 ,  H04L63/0853

Abstract: PURPOSE: A high-speed hardware cryptographic processing system and a method thereof are provided to enhance the performance of a cryptographic process by performing a symmetric key and an asymmetric key ciphering algorithm in parallel. CONSTITUTION: A scheduler(120) is used for generating the scheduling information for an executing procedure of a ciphering algorithm. A storage portion(130) stores rearranged command, rearrangement information, and the address information of the cryptographic data according to the scheduling information. A cryptographic processing portion(150) reads the stored data of the storage portion and performs a cryptographic process according to the command priority by referring to the command rearrangement information and the address information. A control portion(140) outputs a command to generate the scheduling information, sort cryptographic data, assign the data, and perform the cryptographic process.

Abstract translation: 目的：提供一种高速硬件加密处理系统及其方法，用于通过并行执行对称密钥和非对称密钥加密算法来增强密码处理的性能。 构成：调度器（120）用于生成用于加密算法的执行过程的调度信息。 存储部（130）根据调度信息存储重新排列的命令，重排信息和密码数据的地址信息。 加密处理部（150）通过参照命令重排信息和地址信息读取存储部分的存储数据，并根据命令优先级执行密码处理。 控制部（140）输出生成调度信息的命令，分类密码数据，分配数据，进行密码处理。

公开(公告)号：KR1020030009597A

公开(公告)日：2003-02-05

申请号：KR1020010044113

申请日：2001-07-23

Applicant: 한국전자통신연구원

Inventor： 김무섭 ,  최용제 ,  김호원 ,  박영수

IPC: G06K19/07

Abstract: PURPOSE: A power supply unit for an IC card and a method for controlling the same are provided to minimize an electric power consumption necessary for driving a system and perform a stable operation in an IC card system having an internal power source(battery). CONSTITUTION: An internal power source(110) supplies a power source of a predetermined level in the case that an internal circuit unit(200) of a card system is an operation mode or a waiting mode. A switching control circuit unit(120) receives a mode judgement signal from a mode judgement unit in the internal circuit unit(200) which judges whether the card system is an operation mode or a waiting mode, and supplies a switching control signal to the first switching unit(140) and the second switching unit(141) in accordance with the received mode judgement signal, respectively. That is, in the case that the card system is an operation mode, the switching control circuit unit(120) supplies a switching control signal to the first switching unit(140) for making the internal power source(110) be supplied to the internal circuit unit(200) and making the internal power source(110) be accumulated in an electric charge accumulating circuit unit(130). Also, the switching control circuit unit(120) supplies a switching control signal to the second switching unit(141) for making an electric charge be accumulated in an electric charge accumulating circuit unit(130).

Abstract translation: 目的：提供用于IC卡的电源单元及其控制方法，以最小化驱动系统所需的电力消耗并在具有内部电源（电池）的IC卡系统中执行稳定的操作。 构成：在卡系统的内部电路单元（200）是操作模式或等待模式的情况下，内部电源（110）提供预定电平的电源。 开关控制电路单元（120）从内部电路单元（200）中的模式判断单元接收模式判断信号，判定卡系统是操作模式还是等待模式，并将切换控制信号提供给第一 切换单元（140）和第二切换单元（141）。 也就是说，在卡系统是操作模式的情况下，切换控制电路单元（120）向第一切换单元（140）提供切换控制信号，以使内部电源（110）提供给内部 电路单元（200），并且使内部电源（110）累积在电荷累积电路单元（130）中。 此外，切换控制电路单元（120）向第二切换单元（141）提供切换控制信号，以在电荷累积电路单元（130）中累积电荷。