公开(公告)号：US12148390B2

公开(公告)日：2024-11-19

申请号：US17962239

申请日：2022-10-07

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Jung Yen Huang

IPC: G09G3/3266 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/3291

Abstract: A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

公开(公告)号：US20240127758A1

公开(公告)日：2024-04-18

申请号：US18322406

申请日：2023-05-23

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Hassan Edrees

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/0247

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

公开(公告)号：US20240127754A1

公开(公告)日：2024-04-18

申请号：US18532835

申请日：2023-12-07

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Hung Sheng Lin ,  Shih Chang Chang ,  Shinya Ono

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/12 ,  H01L29/786

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/1225 ,  H01L29/78651 ,  H01L29/7869 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0202 ,  G09G2320/0295 ,  G09G2320/043

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

公开(公告)号：US20240086014A1

公开(公告)日：2024-03-14

申请号：US18514934

申请日：2023-11-20

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Donggeon Han ,  Jason N Gomez ,  Kyung Wook Kim ,  Nikolaus Hammler ,  Pei-En Chang ,  Saman Saeedi ,  Shih Chang Chang ,  Shinya Ono ,  Suk Won Hong ,  Szu-Hsien Lee ,  Victor H Yin ,  Young-Jik Jo ,  Yu-Heng Cheng ,  Joyan G Sanctis ,  Hongwoo Lee

IPC: G06F3/041 ,  G06F3/044 ,  H10K59/40

CPC classification number: G06F3/04182 ,  G06F3/044 ,  H10K59/40 ,  G06F3/0412 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

公开(公告)号：US20230237965A1

公开(公告)日：2023-07-27

申请号：US18192905

申请日：2023-03-30

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L29/786 ,  H10K59/121

CPC classification number: G09G3/3258 ,  H01L29/7869 ,  H10K59/1213 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US20230206848A1

公开(公告)日：2023-06-29

申请号：US18172049

申请日：2023-02-21

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Hung Sheng Lin ,  Shih Chang Chang ,  Shinya Ono

IPC: G09G3/3233 ,  H01L29/786 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L29/78651 ,  H01L29/7869 ,  G09G3/3266 ,  G09G3/3275 ,  H01L27/1225 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0295 ,  G09G2310/0202 ,  G09G2320/043

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

公开(公告)号：US20230042963A1

公开(公告)日：2023-02-09

申请号：US17970842

申请日：2022-10-21

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

公开(公告)号：US20230035245A1

公开(公告)日：2023-02-02

申请号：US17962239

申请日：2022-10-07

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Jung Yen Huang

IPC: G09G3/3266 ,  G09G3/20 ,  G09G3/3291

Abstract: A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.

公开(公告)号：US20220180819A1

公开(公告)日：2022-06-09

申请号：US17501530

申请日：2021-10-14

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Zino Lee ,  Chun-Chieh Lin ,  Chen-Ming Chen

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

公开(公告)号：US20220180812A1

公开(公告)日：2022-06-09

申请号：US17680059

申请日：2022-02-24

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.