公开(公告)号：US20190228726A1

公开(公告)日：2019-07-25

申请号：US16369319

申请日：2019-03-29

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Zino Lee ,  Gihoon Choo ,  Hassan Edrees ,  Chin-Wei Lin

IPC: G09G3/36 ,  G09G3/3225

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

公开(公告)号：US20250131885A1

公开(公告)日：2025-04-24

申请号：US18407578

申请日：2024-01-09

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Hassan Edrees

IPC: G09G3/3266 ,  G11C19/28

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

公开(公告)号：US11922887B1

公开(公告)日：2024-03-05

申请号：US17368472

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chuan-Jung Lin ,  Gihoon Choo ,  Hassan Edrees ,  Hei Kam ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3275 ,  H10K59/121 ,  H10K59/126 ,  H10K59/131

CPC classification number: G09G3/3275 ,  H10K59/1213 ,  H10K59/1216 ,  H10K59/126 ,  H10K59/131 ,  G09G2320/0214

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

公开(公告)号：US20240036680A1

公开(公告)日：2024-02-01

申请号：US18323659

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Suhwan Moon ,  Dong-Gwang Ha ,  Jiaxi Hu ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Hassan Edrees ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Chin-Wei Lin ,  Kyung Wook Kim

IPC: G06F3/041 ,  G09G3/3208 ,  G06F3/044

CPC classification number: G06F3/04184 ,  G06F3/0412 ,  G09G3/3208 ,  G06F3/0446 ,  G06F3/0444 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

公开(公告)号：US11211020B2

公开(公告)日：2021-12-28

申请号：US16369319

申请日：2019-03-29

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Zino Lee ,  Gihoon Choo ,  Hassan Edrees ,  Chin-Wei Lin

IPC: G09G3/36 ,  G09G3/3225 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/3266

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

公开(公告)号：US20240127758A1

公开(公告)日：2024-04-18

申请号：US18322406

申请日：2023-05-23

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Hassan Edrees

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2320/0247

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

公开(公告)号：US11127357B2

公开(公告)日：2021-09-21

申请号：US16850936

申请日：2020-04-16

Applicant: Apple Inc.

Inventor： Jie Won Ryu ,  Myungjoon Choi ,  Hyunsoo Kim ,  Hyunwoo Nho ,  Chin-Wei Lin ,  Shiping Shen ,  Kingsuk Brahma ,  Chaohao Wang ,  Shinya Ono ,  Alex H. Pai ,  Hassan Edrees

IPC: G09G3/30 ,  G09G3/3291

Abstract: Techniques for implementing and/or operating an electronic device, which includes a display pixel that emits light to facilitate displaying an image during an emission period and a data driver coupled to the display pixel via a data line. The data driver generates a data line voltage signal based on image data that indicates target luminance of the display pixel in the image and supplies the data line voltage signal to the data line during a non-emission period preceding the emission period to facilitate writing the image to the display pixel. Additionally, the data driver supplies an intermediate voltage greater than a ground voltage to the data line during the emission period in which the image is displayed to facilitate reducing luminance variation in the image resulting from a leakage current flowing between an internal node of the display pixel and the data line during the emission period.

公开(公告)号：US11049457B1

公开(公告)日：2021-06-29

申请号：US16852234

申请日：2020-04-17

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Chun-Chieh Lin ,  Gihoon Choo ,  Hassan Edrees ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.

公开(公告)号：US20200335046A1

公开(公告)日：2020-10-22

申请号：US16850936

申请日：2020-04-16

Applicant: Apple Inc.

Inventor： Jie Won Ryu ,  Myungjoon Choi ,  Hyunsoo Kim ,  Hyunwoo Nho ,  Chin-Wei Lin ,  Shiping Shen ,  Kingsuk Brahma ,  Chaohao Wang ,  Shinya Ono ,  Alex H. Pai ,  Hassan Edrees

IPC: G09G3/3291

Abstract: Techniques for implementing and/or operating an electronic device, which includes a display pixel that emits light to facilitate displaying an image during an emission period and a data driver coupled to the display pixel via a data line. The data driver generates a data line voltage signal based on image data that indicates target luminance of the display pixel in the image and supplies the data line voltage signal to the data line during a non-emission period preceding the emission period to facilitate writing the image to the display pixel. Additionally, the data driver supplies an intermediate voltage greater than a ground voltage to the data line during the emission period in which the image is displayed to facilitate reducing luminance variation in the image resulting from a leakage current flowing between an internal node of the display pixel and the data line during the emission period.

公开(公告)号：US20240420646A1

公开(公告)日：2024-12-19

申请号：US18815723

申请日：2024-08-26

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Hassan Edrees

IPC: G09G3/3266

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.