公开(公告)号：WO1996032724A1

公开(公告)日：1996-10-17

申请号：PCT/US1996005107

申请日：1996-04-11

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ESTAKHRI, Petro ,  ASSAR, Mahmud

IPC: G11C08/00

CPC classification number: G11C8/12

Abstract: A circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines. A first embodiment includes a plurality of paired address lines; each line in each pair provides a logical complementary signal. Only a selected one of the lines of each pair is coupled to integrated circuit. Each of the integrated circuits is coupled to a unique combination of these selected lines of the pairs. In a second embodiment a select signal is clocked by a controller from one of the integrated circuits to the next in a fashion similar to a shift register. Once the select signal is present in the desired integrated circuit, the controller then provides an enable signal to all the integrated circuits which enables only that desired integrated circuit. In yet another embodiment, the address lines are also used as chip select signal lines, one address line for each integrated circuit. A Chip_select_clock_enable line is used to toggle the chip select signal to the desired device. In a preferred embodiment, a unique value is stored in a register on each integrated circuit. A controller places the unique value of a desired integrated circuit onto a bus. A comparator in each integrated circuit determines which chip has been selected. The controller then provides a chip select signal to activate the desired integrated circuit.

Abstract translation: 提供电路用于选择具有最少数量的芯片选择信号线的多个集成电路芯片之一。 第一实施例包括多个配对地址线; 每对中的每一行提供逻辑互补信号。 每对中仅选择一条线耦合到集成电路。 每个集成电路耦合到这些所选择的线对中的独特组合。 在第二实施例中，选择信号由类似于移位寄存器的方式由控制器从集成电路中的一个向下一个计时。 一旦选择信号存在于期望的集成电路中，则控制器然后向所有集成电路提供使能信号，所述集成电路只能实现所需的集成电路。 在另一个实施例中，地址线还用作片选信号线，每个集成电路用一条地址线。 Chip_select_clock_enable线用于将芯片选择信号切换到所需的器件。 在优选实施例中，唯一值存储在每个集成电路的寄存器中。 控制器将所需集成电路的唯一值放置在总线上。 每个集成电路中的比较器确定选择哪个芯片。 然后，控制器提供芯片选择信号以激活所需的集成电路。

公开(公告)号：WO1996030889A1

公开(公告)日：1996-10-03

申请号：PCT/US1996004334

申请日：1996-03-28

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  EGLIT, Alexander, J.

IPC: G09G01/28

CPC classification number: H04N5/44 ,  G09G1/285 ,  H04N9/641 ,  H04N21/4113

Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.

Abstract translation: 在计算机的图形卡中，提供用于显示由外部电视机上的卡生成的图形呈现的电路。 电视适配器控制CRT控制器的水平状态机，以便延迟CRT定时信号的产生与水平线变化的时间段。 结果，复合视频信号设置有时基可变前沿，以模拟VTR视频信号。 响应于所生成的复合视频信号，电视机切换到VTR模式以禁用用于分离广播电视信号的亮度和色度分量的梳状滤波器。

公开(公告)号：WO1996025794A1

公开(公告)日：1996-08-22

申请号：PCT/US1996001994

申请日：1996-02-15

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  DU, He ,  WANG, Yun-Ti

IPC: H03K03/356

CPC classification number: G11C7/065 ,  G11C7/062

Abstract: A sense amplifier circuit includes a differential input circuit which receives first and second data inputs, din1 and din2, and generates, in response to a first control signal PHI 1 being active LOW, a differential voltage across first and second nodes, which is indicative of a voltage difference between the first and second data inputs, din1 and din2; a pull-up circuit which connects, in response to a second control signal PHI 2 being active LOW, a high voltage reference Vdd to both the first and second nodes; a latching circuit which generates and latches, in response to voltages provided on the first and second nodes by the differential input and pull-up circuits, first and second latched data outputs; and an equalization circuit which equalizes, in response to a third control signal PHI 0 being active LOW, voltages on data lines respectively connected to the first and second data outputs. Timing of the first and second control signals, PHI 1 and PHI 2, is such that the second control signal PHI 2 is activated LOW after a finite period following the initial activation of the first control signal PHI 1. The third control signal PHI 0 is preferably activated LOW when the first and second control signals, PHI 1 and PHI 2, are inactive HIGH.

Abstract translation: 读出放大器电路包括差分输入电路，其接收第一和第二数据输入din1和din2，并且响应于第一控制信号PHI 1为低电平而产生跨第一和第二节点的差分电压，其表示 第一和第二数据输入端之间的电压差din1和din2; 上拉电路，响应于第二控制信号PHI 2为有效LOW，将高电压参考值Vdd连接到第一和第二节点; 锁存电路，响应于由差分输入和上拉电路在第一和第二节点上提供的电压而产生和锁存第一和第二锁存数据输出; 以及均衡电路，其响应于第三控制信号PHI 0为低电平而均衡，分别连接到第一和第二数据输出的数据线上的电压。 第一和第二控制信号PHI 1和PHI 2的定时使得在第一控制信号PHI 1的初始激活之后的有限时间段之后，第二控制信号PHI 2被激活为低电平。第三控制信号PHI 0是 当第一和第二控制信号PHI 1和PHI 2处于非活动状态时，优选地被激活为低电平。

公开(公告)号：WO1996021274A1

公开(公告)日：1996-07-11

申请号：PCT/US1996000393

申请日：1996-01-05

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ZHANG, Zhong-Xuan ,  LIN, Jyhfong ,  WANG, Yun-ti

IPC: H03K17/041

CPC classification number: H03K17/6874 ,  H03K17/04106 ,  H03K2217/0036

Abstract: A high speed CMOS current switching circuit suitable for use in digital to analog converters for graphic interfaces having high pixel clock rates, and such interfaces as may be used in portable and other battery operated or low power consumption applications. In operation, the current switching circuit normally steers an idle current to ground. If the bit of the digital to analog converter input digital signal represented by the respective source is a 1, the input signal representing the bit is delayed slightly while the current steered to ground is increased from the idle value to the full desired output current, whereupon at the end of the delay, the device coupling the output current to ground is turned off, thereby forcing the output current through an output device. A low power current steering circuit which can perform dynamic current steering without affecting switching speed performance is also disclosed. During the mode 'off', the path from current source to ground is completely cut off, so that at this mode there is no power consumption. Prior to turning to the 'on' mode, the current source IB (M13) is first turned on (M14) to establish a stable current and to bias all the related nodes. The current steering circuitry (M11, M12) is then turned to mode 'on' to achieve a smooth transition. Similarly, the transition from mode 'on' to 'off' is achieved by steering the current to ground first and then cutting off the current source. Various embodiments are disclosed.

Abstract translation: 适用于具有高像素时钟速率的图形接口的数模转换器的高速CMOS电流开关电路，以及可用于便携式和其他电池供电或低功耗应用的接口。 在操作中，电流开关电路通常将空闲电流引导到地。 如果由相应源表示的数模转换器输入数字信号的位为1，则表示位的输入信号被稍微延迟，而转向地的电流从空值增加到完全期望的输出电流，于是， 在延迟结束时，将输出电流耦合到地的器件被关断，从而迫使输出电流通过输出器件。 还公开了一种能够执行动态电流转向而不影响开关速度性能的低功率电流转向电路。 在模式“关闭”期间，从电流源到地的路径被完全切断，因此在这种模式下不存在功耗。 在进入“开”模式之前，首先打开电流源IB（M13）（M14）以建立稳定电流并偏置所有相关节点。 当前的转向电路（M11，M12）然后转为“开”模式以实现平稳过渡。 类似地，通过首先将电流转向地面然后切断电流来实现从模式“开”到“关”的转换。 公开了各种实施例。

公开(公告)号：WO1996019078A1

公开(公告)日：1996-06-20

申请号：PCT/US1995015618

申请日：1995-12-14

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ROSENAU, Mark, A. ,  SARTAIN, Daryl ,  DAUM, Daniel ,  ORT, Jeffrey, G.

IPC: H04N07/12

CPC classification number: H04N9/8216 ,  G09G5/393 ,  G11B20/00007 ,  G11B20/10527 ,  G11B27/10 ,  G11B27/105 ,  G11B27/3027 ,  G11B27/3036 ,  G11B2220/213 ,  G11B2220/2545 ,  H04N5/775 ,  H04N5/85 ,  H04N9/8042 ,  H04N9/8063 ,  H04N9/87 ,  H04N19/132 ,  H04N19/42 ,  H04N19/423 ,  H04N19/427 ,  H04N19/587 ,  H04N19/61 ,  H04N21/4143 ,  H04N21/4305 ,  H04N21/4307

Abstract: A multimedia system includes an integrated system and video decoder with an audio/video synchronization circuit (200) for substantially synchronizing the display of video images with audio playback. An audio presentation time stamp (APTS) (415) is detected in the compressed/coded audio data stream in the integrated system and video decoder and stored in a data latch (442). The compressed/coded audio data stream is fed to an audio decoder which decodes/decompresses the audio data and outputs an audio signal. The audio decoder detects when audio data corresponding to an APTS (415) had been output and sets a corresponding flag (213). The flag (213) indicates to the integrated system and video decoder that a corresponding audio segment had been decoded/decompressed and output. The integrated system and video decoder then synchronizes the video output with the audio output by repeating or skipping frames of video data.

Abstract translation: 多媒体系统包括具有音频/视频同步电路（200）的集成系统和视频解码器，用于使视频图像的显示与音频回放基本上同步。 音频呈现时间戳（APTS）（415）在集成系统和视频解码器中的压缩/编码音频数据流中被检测并存储在数据锁存器（442）中。 压缩/编码的音频数据流被馈送到音频解码器，音频解码器解码/解压缩音频数据并输出音频信号。 音频解码器检测与APTS（415）相对应的音频数据是否已被输出并设置相应的标志（213）。 标志（213）向集成系统和视频解码器指示对应的音频片段已被解码/解压缩并输出。 然后，集成系统和视频解码器通过重复或跳过视频数据帧来同步视频输出与音频输出。

公开(公告)号：WO1996015538A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014307

申请日：1995-11-06

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  CROSS, Randolph, A.

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C29/24 ,  G11C29/88

Abstract: A data processing system (100) is provided which includes a memory (104), an array (204) of memory cells arranged in rows and columns, each row being addressable by an address. Address generation circuitry (201/202) is provided for generating ones of the addresses for accessing selected ones of the rows in the array (204). An associated memory (203) is coupled to the address generation circuitry (201/202) for translating a first address, received from the address generation circuitry (201/202) and addressing a defective one of the rows of the array (204), into a second address addressing an operative one of the rows in array (204), the second address being sent to the memory.

Abstract translation: 提供了一种数据处理系统（100），其包括存储器（104），以行和列布置的存储器单元的阵列（204），每行可由地址寻址。 地址生成电路（201/202）被提供用于生成用于访问阵列（204）中的所选行的地址的那些地址。 相关联的存储器（203）耦合到地址产生电路（201/202），用于转换从地址产生电路（201/202）接收的第一地址和寻址阵列（204）的行中的有缺陷的一个， 转换成寻址阵列（204）中的一行中的可操作的一行的第二地址，该第二地址被发送到该存储器。

公开(公告)号：WO1996010826A1

公开(公告)日：1996-04-11

申请号：PCT/US1995012903

申请日：1995-09-29

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  RUNAS, Michael, E.

IPC: G11C07/00

CPC classification number: G11C7/1021 ,  G11C7/1039

Abstract: A memory (200) is provided which includes an array (201) of volatile memory cells (202). Addressing circuitry (205, 213) is included for providing access to selected ones of the memory cells (202). Master read/write circuitry (208) is included for reading and writing data into the selected memory cells (202). First slave circuitry (210, 211) is provided for storing data for exchange with the master read/write circuitry (208). Second slave circuitry (210/211) is also provided for storing data for exchange with the master read/write circuitry (208). Control circuitry (206, 214, 215) controls the exchanges of data between the master read/write circuitry (208) and the first and second slave circuitry (210, 211).

Abstract translation: 提供了包括易失性存储单元（202）的阵列（201）的存储器（200）。 包括寻址电路（205,213），用于提供对所选存储单元（202）的访问。 包含主读/写电路（208）用于将数据读入和写入所选存储单元（202）。 提供第一从属电路（210,211）用于存储用于与主读/写电路（208）交换的数据。 还提供第二从属电路（210/211）用于存储用于与主读/写电路（208）交换的数据。 控制电路（206,214,215）控制主读/写电路（208）与第一和第二从电路（210,211）之间的数据交换。

公开(公告)号：WO1995030220A1

公开(公告)日：1995-11-09

申请号：PCT/US1995005259

申请日：1995-04-28

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  BINDLISH, Rakesh, Kumar ,  BRIL, Vlad ,  EGLIT, Alexander

IPC: G09G05/14

CPC classification number: G09G5/14 ,  G09G2340/125 ,  H04N5/45

Abstract: A computer video controller, particularly a VGA or SVGA video controller for use with graphical user interface (GUI) software such as WINDOWS3 or OS/23 is provided with two video data pipelines for simultaneously displaying full motion video within a window in a video display. A first data pipeline displays background video at a first pixel depth. A second data pipeline is provided to display a motion video window at a second, usually higher, pixel depth. The location of the motion video window is measured horizontally in number of memory fetch cycles needed to retrieve the horizontal scan line of pixel data abutting the motion video window. The width of the motion video window is measured in the number of memory fetches required to retrieve one scan line of the motion video window. By providing two parallel data pipelines having equal delays, the motion video window can be generated by selectively retrieving background pixel data or motion video window pixel data and transferring the data to the appropriate pipeline. In an alternative embodiment, data tags may be used to distinguish between background and motion video window pixel data. The controller may also support various compression formats for motion video.

Abstract translation: 具有用于诸如WINDOWS3或OS / 23之类的图形用户界面（GUI）软件的VGA或SVGA视频控制器的计算机视频控制器具有两个视频数据流水线，用于在视频显示器的窗口内同时显示全部运动视频。 第一数据流水线以第一像素深度显示背景视频。 提供第二数据流水线以在第二通常较高的像素深度处显示运动视频窗口。 水平地测量运动视频窗口的位置以检索与运动视频窗口相邻的像素数据的水平扫描行所需的存储器提取周期数。 以检索运动视频窗口的一条扫描线所需的存储器提取量来测量运动视频窗口的宽度。 通过提供具有相等延迟的两个并行数据流水线，可以通过选择性地检索背景像素数据或运动视频窗口像素数据并将数据传送到适当的流水线来生成运动视频窗口。 在替代实施例中，可以使用数据标签来区分背景和运动视频窗口像素数据。 控制器还可以支持用于运动视频的各种压缩格式。

公开(公告)号：WO1995024035A1

公开(公告)日：1995-09-08

申请号：PCT/US1995002608

申请日：1995-03-03

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  NEMAZIE, Siamack ,  HO, Son, H.

IPC: G11B20/12

CPC classification number: G11B27/3027 ,  G11B5/596 ,  G11B20/10 ,  G11B20/1258 ,  G11B2020/1234 ,  G11B2020/1282 ,  G11B2020/1284

Abstract: A table driven method and apparatus for automatic split field processing in a disk drive system stores data representing the split fields after each servo mark of a frame. Each track of the disk drive system is divided up into frames or groups of sectors or equivalently servo marks, each frame comprising a predetermined number N of sectors and a predetermined number M of servo marks. Beginning from the INDEX mark, after every N sectors or equivalently M servo marks, the next sector must start after the next servo mark. The value N is a constant within each zone on a disk but can vary from zone to zone as the storage density changes. The information for each servo mark within a frame is stored in a frame table in the buffer memory (7). A starting address pointer (FTSAP) and an ending address pointer (FTEAP) are used to keep track of the starting and ending addresses, respectively, of the frame table. An address pointer (FTAP) is used to point to the current entry of interest in the frame table. For each servo mark within the frame, a sector pulse counter (24) is stored, representing the number of sector pulses between the current servo mark and the next servo mark. A first time delay DY1, representing the delay from the current servo mark to the first sector pulse to be generated and a second delay value DYS, representing the size of the last split field before the next servo mark are also stored.

Abstract translation: 用于盘驱动系统中的自动分割场处理的表驱动方法和装置在帧的每个伺服标记之后存储表示分割场的数据。 磁盘驱动器系统的每个磁道被划分成帧或组的组或等效的伺服标记，每个帧包括预定数量的N个扇区和预定数量的M个伺服标记。 从INDEX标记开始，在每N个扇区或等效的M个伺服标记之后，下一个扇区必须在下一个伺服标记之后开始。 值N是磁盘上每个区域内的常数，但随着存储密度的变化，它可以随区域而变化。 帧中的每个伺服标记的信息被存储在缓冲存储器（7）中的帧表中。 起始地址指针（FTSAP）和结束地址指针（FTEAP）分别用于跟踪帧表的开始和结束地址。 地址指针（FTAP）用于指向帧表中感兴趣的当前条目。 对于帧内的每个伺服标记，存储扇区脉冲计数器（24），表示当前伺服标记和下一个伺服标记之间的扇区脉冲数。 表示从当前伺服标记到要产生的第一扇区脉冲的延迟的第一延迟DY1和表示下一个伺服标记之前的最后一个分割场的大小的第二延迟值DYS也被存储。

公开(公告)号：WO1995010083A1

公开(公告)日：1995-04-13

申请号：PCT/US1994010803

申请日：1994-09-23

Applicant: CIRRUS LOGIC, INC.

Inventor： CIRRUS LOGIC, INC. ,  ASSAR, Mahmud ,  ESTAKHRI, Petro ,  NEMAZIE, Siamack ,  MOZAFFARI, Mahmood

IPC: G06F12/02

CPC classification number: G11C16/105 ,  G06F3/0601 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2003/0694 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211 ,  G11C16/102 ,  G11C16/349 ,  G11C16/3495

Abstract: A semiconductor mass storage system can be substituted for a rotating hard disk. The system avoids an erase cycle each time information stored in the mass storage is changed by programming any changed data file into an empty mass storage block rather than over itself. Periodically the mass storage will need to be cleaned up. Even use of all blocks is provided by using several flags (622-628), a map to correlate a logical address of a block to a physical address (630) and a count register (620) for each block. Flags indicate defective blocks (624), used blocks (626), old versions of a block (628), and erase inhibit (622). A counter (620) is used to determine the amount a block has been erased and written. Reading is performed by providing a logical address and sequentially comparing it with the mapped logical addresses.

Abstract translation: 半导体大容量存储系统可以代替旋转硬盘。 每当通过将任何改变的数据文件编程为空的大容量存储块而不是在其本身上改变时，每次存储在大容量存储器中的信息都可以避免擦除循环。 定期对大容量存储进行清理。 通过使用几个标志（622-628）提供所有块的均匀使用，映射将块的逻辑地址与物理地址（630）和每个块的计数寄存器（620）相关联。 标志指示有缺陷块（624），使用块（626），块的旧版本（628）和擦除禁止（622）。 计数器（620）用于确定块被擦除和写入的量。 通过提供逻辑地址并将其顺序与映射的逻辑地址进行比较来执行读取。