公开(公告)号：JPH09311662A

公开(公告)日：1997-12-02

申请号：JP12856696

申请日：1996-05-23

Applicant: FUJITSU LTD

Inventor： ISHIDA KATSUHIRO ,  TAJIMA MASAYA ,  UEDA TOSHIO ,  KURIYAMA HIROHITO ,  YAMAMOTO AKIRA

IPC: G09G3/28 ,  G09G3/20 ,  G09G3/288 ,  G09G3/291 ,  G09G3/294

Abstract: PROBLEM TO BE SOLVED: To suppress a color false outline phenomenon when a dynamic image is displayed by means of an in-frame time-sharing type half-tone display method. SOLUTION: In the half-tone display method in a display method in which a display screen is constructed of a plurality of cells, data displayed in each cell is rewritten for every frame, and luminance of each cell is decided on the basis of a light quantity radiated from the cell during one frame equivalent duration, one frame is divided into a plurality of subframes, and a subframe radiating light and a subframe radiating no light are combined together so as to indicate a half tone. In this case, the subframes whose luminances satisfy a relationship Nn=Nn-1+Nn-2 are provided when luminances of a plurality of the subframes are Nn, Nn-1, Nn-2,..., N1 in the luminance order from the most intensity one.

公开(公告)号：JPH08211848A

公开(公告)日：1996-08-20

申请号：JP1798995

申请日：1995-02-06

Applicant: FUJITSU LTD

Inventor： UEDA TOSHIO ,  ISHIDA KATSUHIRO

IPC: G09G3/291 ,  G09G3/20 ,  G09G3/28

Abstract: PURPOSE: To improve the display quality of a dynamic image part by displaying display data by frame interpolation every subframe by using new, specified and individual motion vectors to improve the halftone disturbance of a chrominance spurious profile part, etc., to be generated in the dynamic image part. CONSTITUTION: The moving direction in-between frames of display data is detected in a motion vector detecting means 6 by comparing the display data inputted in the frame in a prescribed frame with the display frame inputted before one frame. Correction values obtained by dividing the delay time from a leading subframe in the frame by a frame cycle are calculated in a motion calculating means 7 and then motion amounts for every subframe are calculated. Then, a frame interpolation means 10 generates new data in which display positions are moved every subframe to a motion display means 9 moving display data positions by the set values of an image display position setting means 8 setting displays from the calculated motion amounts and then display operations are executed based on display data for every subframe.

公开(公告)号：JPH07140927A

公开(公告)日：1995-06-02

申请号：JP29088193

申请日：1993-11-19

Applicant: FUJITSU LTD

Inventor： KURIYAMA HIROHITO ,  UEDA TOSHIO ,  KANEKO KEIICHI ,  YAMAMOTO AKIRA

IPC: H04N5/66 ,  G09G3/20 ,  G09G3/288 ,  G09G3/291 ,  G09G3/292 ,  G09G3/294 ,  G09G3/296 ,  G09G3/298 ,  H04N5/70 ,  H04N9/20 ,  G09G3/28

Abstract: PURPOSE:To provide a plane display device provided with a high speed operation processing function capable of instantly displaying an image with stable display quality even when a first line data signal is sent as soon as a frame start signal is received. CONSTITUTION:In a drive control system in the plane display device, further, every divided sub frame is constituted of at least an initialization period S1' initializing a display picture, an address period S2 selecting plural pieces of cell parts and executing the write operation of the proper display data and a maintenance discharge period S3 discharging and light emitting the cell parts written with the display data for a prescribed period, further the plane display device is provided with an initializing operation start point of time control means detecting an input of a display start signal VSYNC of one frame and adjusting the initializing operation start point of time ST of the initialization period S1' so as to become before the input point of time of the frame start signal VSYNC.

公开(公告)号：JPH06180555A

公开(公告)日：1994-06-28

申请号：JP33449892

申请日：1992-12-15

Applicant: FUJITSU LTD

Inventor： NAGAOKA YOSHIMASA ,  KANAZAWA GIICHI ,  UEDA TOSHIO

IPC: G09G3/20

Abstract: PURPOSE:To provide a color display device having a countermeasure by which the existence of a color cell which is broken or whose light emission gets faulty is easily detected and the color display of an entire display picture is not adeversely affected even though the color cell which is broken or whose light emission gets faulty exists. CONSTITUTION:This color display device 1 is constituted of a color display board 6 where plural picture element parts 5 consisting of at least three color cells 2-4 developing different kinds of colors are arranged in a matrix state, an image input means 7, a picture element address means 8, a picture element driver means 9, a color cell driver means 10 and a display control means 11 controlling the respective means; and it is provided with a picture element function inspecting mode setting means 12, a means 13 for detecting the light emitting state of the respective color cells 2-4, a means 14 for discriminating the faulty state of the light emission of the color cells, and a storage means 15 storing the address of the picture element part 5 and information on the kind of color in the case of judging that the color emission of at least one color cell gets faulty.

公开(公告)号：JPH05165428A

公开(公告)日：1993-07-02

申请号：JP33231091

申请日：1991-12-16

Applicant: FUJITSU LTD

Inventor： KURIYAMA HIROHITO ,  KANEKO KEIICHI ,  UEDA TOSHIO

IPC: G09G3/288 ,  G09G3/20 ,  G09G3/291 ,  G09G3/296 ,  H04N5/66

Abstract: PURPOSE:To provide a display device capable of suppressing a loss current when a capacitor is charged/discharged and generating a stable write voltage without depending on the frequency of a write voltage as a display device to display a character and a graphic, etc., by using a plasma display panel. CONSTITUTION:The emitter voltage of a transistor Tr2 is taken out as an auxiliary voltage Valpha, and is accumulated in a first capacitor C10. The auxiliary voltage Valpha, after being changed to a second detection voltage betaVs by resistors R13, R14, is added on a first detection voltage alphaVs proportional to a source voltage Vs. The addition voltage of the first detection voltage alphaVs and the second detection voltage betaVs is compared with a reference voltage Vr by an error amplifier 41, and the voltage, after being changed to a differential voltage gammaVs, is supplied to the base of a transistor Tr1, which keeps the voltage Valpha constant.

公开(公告)号：JPH05158434A

公开(公告)日：1993-06-25

申请号：JP32214391

申请日：1991-12-05

Applicant: FUJITSU LTD

Inventor： UEDA TOSHIO ,  KURIYAMA HIROHITO ,  KANEKO KEIICHI

IPC: G09G3/288 ,  G09G3/291 ,  G09G3/296

Abstract: PURPOSE:To eliminate a charging current to an interline electrostatic capacity when a cancel pulse is generated and to reduce power consumption of a display device by making the output end of a driving circuit for generating the cancel pulse in a high impedance. CONSTITUTION:In addition to a TSC signal, an SUS signal, an STB signal and POR signal, an enable(ENA) signal is inputted to control circuits 11 and 11' as a control signal. The driving circuit constituted of the control circuits 11 and 11' and switching circuits 109 and 109' is made to be selective in three kinds of states of the high impedance, a high potential side power-supply voltage VDH and a low potential side power-supply voltage GND by the ENA signal in accordance with an input data signal. And in the case that the cancel pulse is outputted after a sustained pulse is outputted as to an X1 electrode driving waveform, the output end of the driving circuit for the X1 electrode is made to be in the high impedance state by the ENA signal when the cancel pulse is outputted, and output of the driving circuit for an X2 electrode is made to be in a GND state. Thus, the charging current to the interline electrostatic capacity is prevented.

公开(公告)号：JPH03269482A

公开(公告)日：1991-12-02

申请号：JP6923990

申请日：1990-03-19

Applicant: FUJITSU LTD

Inventor： UEDA TOSHIO ,  YOSHIKAWA KAZUO

IPC: G09G3/20 ,  G09G3/28 ,  G09G3/2813 ,  G09G3/291 ,  G09G3/292 ,  G09G3/294 ,  G09G3/296

Abstract: PURPOSE:To reduce the power consumption at the time of a high display rate without decreasing the easiness of seeing a display by varying the alternation rate of a high and a low contrast image plane at the time of the high display rate with the display rate signal of a plasma display panel (PDP) based upon an external gradation control signal. CONSTITUTION:A display rate recognition part 4 recognizes the display rate of the PDP according to the external gradation control signal 2 and outputs the display rate signal 3 to a display control part 6. Then the control part 6 generates a display control signal 5 for varying the alternation rate of the high contrast image plane and low contrast image plane to less than one vertical period at the time of the high display rate and outputs the signal to a PDP driving part 7. Consequently, the ratio of the high contrast image plane decreases at the time of the high display rate and the number of light pulses is decreased to reduce the power consumption to half. An intermediate and a low gradation brightness image plane, on the other hand, are controlled so that the number of light pulses does not decrease and the power consumption at the time of the high display rate is reduced to half without decreasing the easiness of seeing the display.

公开(公告)号：JPH03182792A

公开(公告)日：1991-08-08

申请号：JP32295789

申请日：1989-12-12

Applicant: FUJITSU LTD

Inventor： UEDA TOSHIO

IPC: G09G3/296 ,  G09G3/291 ,  G09G3/292 ,  G09G3/294

Abstract: PURPOSE:To autonomously vary the ratio allocation of a high luminance screen mode and a low luminance screen mode in accordance with a display rate and to suppress the power consumption quantity at the time of high display rate by setting the ratio allocation of the high luminance screen mode and the low luminance screen mode, based on a result of decision of a deciding means. CONSTITUTION:The device is provided with a counting means for counting display data from a converting circuit 102 and a display data counter 200 being a deciding means for deciding a display rate of a screen in accordance with a result of counting of the counting means. In such a state, based on a result of decision, a ratio allocation of a high luminance screen mode and a low luminance screen mode is set. Accordingly, the ratio allocation of the high luminance screen mode and the low luminance screen mode can be varied autonomously by the display rate of the screen, and especially, it is set so that the ratio of the low luminance screen mode increases at the time of high display rate. In such a way, the number of object cells to which a discharge maintaining pulse is applied at the time of high display rate decreases and the power consumption quantity can be suppressed.

公开(公告)号：JPH03171194A

公开(公告)日：1991-07-24

申请号：JP31252589

申请日：1989-11-30

Applicant: FUJITSU LTD

Inventor： UEDA TOSHIO

IPC: G09G3/291 ,  G09G3/292 ,  G09G3/294 ,  G09G3/296

Abstract: PURPOSE:To decrease loss currents so as to suppress a power loss and to reduce electric power consumption by interposing a constant current element between a voltage line for maintenance pulses and a resistance voltage dividing circuit so that the supply current to the resistance voltage dividing circuit for generating a writing voltage is maintained constant. CONSTITUTION:The constant current element 201A is interposed between the voltage line L 10 for the maintenance pulses VS and the resistance voltage dividing circuit 102. The current flowing from the voltage line L 10 for the maintenance pulses VS to the 2nd resistance voltage dividing circuit 102 is held constant in such a manner and, therefore, the current flowing to a 1st transistor Q 10 is confined only to the current derived from the excess voltage of a 1st capacitor as a power source. The loss currents are eliminated in this way, by which the power loss is averted and the electric power consumption is reduced.

公开(公告)号：JPH01237691A

公开(公告)日：1989-09-22

申请号：JP6364388

申请日：1988-03-18

Applicant: FUJITSU LTD

Inventor： KAMEYAMA SHIGEKI ,  KARIYA NORIJI ,  TANIOKA TAKESHI ,  TANAHASHI RIKURO ,  UEDA TOSHIO

IPC: G06F3/147 ,  G09G1/00 ,  G09G1/02 ,  G09G3/20 ,  G09G3/28 ,  G09G3/288 ,  G09G3/291 ,  G09G3/293 ,  G09G3/294 ,  G09G3/296 ,  G09G5/00

Abstract: PURPOSE:To simplify the constitution of system hardware by switching a sustain mode to a write mode to change the display content of one image plane only at the time of changing the image of a display device. CONSTITUTION:An address line Ax of an EPROM 4 is changed from a low level to a high level so that the write data is selected only when a W.END signal indicating the end of the data feeding is supplied by a driving control signal generating circuit 5, i.e., only when the image of the display device is to be changed. The sustain mode is set and the same display content is continuously displayed by utilizing the memory function of the display device so that the image of the display device is maintained if there is no need for changing the image of the display device. The need for display control circuits such as video RAM, refresh counter and multiplexer is thereby eliminated and the constitution of the system hardware is simplified.