公开(公告)号：JPH04345255A

公开(公告)日：1992-12-01

申请号：JP11821991

申请日：1991-05-23

Applicant: FUJITSU LTD

Inventor： MATSUDA MASAHIRO

IPC: G03G21/00 ,  G03G15/00 ,  H04M11/00 ,  H04N1/00 ,  H04N1/32

Abstract: PURPOSE:To display the idle/busy state simultaneously onto telephone sets in a telephone network with respect to the confirmation of the idle/busy state of common equipment such as copying machines or common places such as conference rooms. CONSTITUTION:An input interface 23 receiving idle/busy information as to a common equipment and place to a telephone set and a display device 11 displaying idle/busy information are provided to the network, to which an idle/ busy information table 16 storing idle/busy information to the exchange is provided.

公开(公告)号：JPH04287141A

公开(公告)日：1992-10-12

申请号：JP5181091

申请日：1991-03-18

Applicant: FUJITSU LTD ,  FUJITSU KYUSHU TSUSHIN SYST KK

Inventor： MATSUDA MASAHIRO ,  IWASAKI KOJI ,  YAMADA HIROTOSHI ,  IKEDA ISAO

IPC: G06F12/00 ,  G06F13/00 ,  G06F15/16 ,  G06F15/177

Abstract: PURPOSE:To share a file preserved at each computer without loading much burden to a user and the computer concerning the file managing system at an information processing system connecting the plural computers by a communication network. CONSTITUTION:A file managing mechanism 300 is provided to totally register respective shared file information in the case of sharing the file preserved at each computer 200 by the other computer, and the file managing mechanism is equipped with a shared file name overlapping monitoring means 301 to inspect registered file names so as not to be overlapped one and another, access control means 302 to record the access condition and current access state of the shared file and to judge the possibility of requested access, reference information collecting means 303 to collect access information to the shared file, and edition number information managing means 304 to report it to the computer that the file is revised while the same computer accesses the same file.

公开(公告)号：JPH03292034A

公开(公告)日：1991-12-24

申请号：JP9426690

申请日：1990-04-10

Applicant: FUJITSU LTD

Inventor： HATANAKA MASAYO ,  KIJIMA YUJI ,  MATSUDA MASAHIRO

IPC: H04M1/60

Abstract: PURPOSE:To attain complete hand-free conversation in response to the operating state by adjusting an output voice signal automatically in response to an input voice level of a talker and selecting the setting of the changeover switch so as to adjust the output voice signal automatically reverse to the input voice level of the talker. CONSTITUTION:A stationary type communication terminal equipment 24 is incorporated with a microphone 10 receiving a voice signal of a talker of a terminal equipment, an amplifier 12 amplifying the received voice signal of the opposite party and a speaker 14 outputting the amplified voice signal. The voice signal of the opposite party outputted from a voice output speaker 14 is adjusted automatically depending on the voice level inputted from a voice input microphone 10. When a switch 20 for switching the control direction is provided, the output level of the voice output speaker 14 is set reverse to the voice level inputted from the input voice microphone 10.

公开(公告)号：JPS63301642A

公开(公告)日：1988-12-08

申请号：JP15903987

申请日：1987-06-26

Applicant: FUJITSU LTD

Inventor： TAZAKI KENJI ,  FUKUDA HARUKI ,  MATSUDA MASAHIRO ,  AWAZU TOMOHIKO ,  HIGUCHI MASAHIRO

IPC: H04L12/43

Abstract: PURPOSE:To obtain a high speed and large capacity by parallely transmitting plural packets without changing the transmitting speed of the packets. CONSTITUTION:A transmitting data stream to flow in is assembled to plural packets with a packet assembling circuit 29 and the respective packets are accommodated to transmitting buffers 25-28 so as to keep the order of the transmitting data stream. By change-over of a switch 24 with the control of a packet processing circuit 23, while an order in these transmitting buffers 25-28 is kept, the packets are sent to transmitting paths S1-S4. In a packet processing circuit 23' while an order on the transmitting paths S1-S4 is kept, the packets are accommodated to receiving buffers 25'-28' in the same order as the accommodating order in the transmitting buffers 25-28. In a packet disassembling circuit 29' the order on the receiving buffers 25'-28' is used and the transmitting data stream is re-constituted. Thus, packet transmission can be realized with a high speed and large capacity.

公开(公告)号：JPS6326051A

公开(公告)日：1988-02-03

申请号：JP16804586

申请日：1986-07-18

Applicant: FUJITSU LTD

Inventor： TAZAKI TAKASHI ,  FUKUDA HARUKI ,  MATSUDA MASAHIRO ,  AWAZU TOMOHIKO ,  HIGUCHI MASAHIRO

Abstract: PURPOSE:To maintain periodicity by controlling a discrimination counter provided in a frame, making reservation in a packet having a counter value allotted beforehand for those to be ensured periodicity of data transfer, and making data transfer using the packet after the packet made a round of the loop. CONSTITUTION:A main node 10 updates the discrimination count value of a discrimination count section every time a frame shown in the figure passes the main node 10, and at the same time, sets the count value before update to a counter stack section. When communication band allocation request for making synchronous communication is received from sub-nodes 201-20n, allocation of the frame to the node is made by reporting the discrimination count value of the frame. Each sub-node holds above- mentioned count value, and when the discrimination count value of received frame conformed with the discrimination count value allocated to the sub-node, sets reservation information to a reservation information section of each packet in the frame and reserves each packet for synchronous communication. When the frame made around of the lopp and the discrimination count value of a counter stack section conformed with allotted value, data are set to each reserved packet of the frame, and synchronous communication is performed.

公开(公告)号：JPS6250008B2

公开(公告)日：1987-10-22

申请号：JP22452282

申请日：1982-12-21

Applicant: FUJITSU LTD

Inventor： AZUMA MITSUHIRO ,  TAKEYAMA AKIRA ,  NOJIMA SATOSHI ,  TAZAKI TAKASHI ,  MATSUDA MASAHIRO

IPC: H04L12/42 ,  H04B3/46 ,  H04L12/437

公开(公告)号：JPS62193340A

公开(公告)日：1987-08-25

申请号：JP3375086

申请日：1986-02-20

Applicant: FUJITSU LTD

Inventor： AWAZU TOMOHIKO ,  FUKUDA HARUKI ,  TAZAKI TAKASHI ,  MATSUDA MASAHIRO

IPC: H04L1/22

Abstract: PURPOSE:To detect troubles related to transmission data on a transmission bus with a high precision by introducing a comparing circuit and a few circuits merely. CONSTITUTION:A communication control circuit 21 which controls switching of transmission and reception data to and from a transmission line 13, a reception bus 22 and a transmission bus 23 shared between terminal equipments 25-1 and 25-2, terminal control circuits 24-1 and 24-2 which control switching of transmission and reception data between busses 22 and 23 and terminal equipments 25-1 and 25-2, etc., are incorporated. Each of terminal control circuits 24-1 and 24-2 includes a transmission buffer 31. A comparing circuit 32 has the first comparison input I and the second comparison input II, and the first comparison input I receives transmission data Ds in the transmission buffer 31, and the second comparison input II receives transmission data appearing on the transmission bus 23. If transmission data received by these inputs I and II do not coincide with each other, an alarm ALM is transmitted from the output of the comparing circuit 32.

公开(公告)号：JPS6236942A

公开(公告)日：1987-02-17

申请号：JP17566485

申请日：1985-08-12

Applicant: FUJITSU LTD

Inventor： AWAZU TOMOHIKO ,  FUKUDA HARUKI ,  TAZAKI TAKASHI ,  MATSUDA MASAHIRO

Abstract: PURPOSE:To prevent intermission of synchronizing communication by reserving entirely all slots in the next frame for the use of the synchronizing continuous communication just after the transmission of a control frame so as to adjust the storage data quantity of a transmission buffer during the passing of the control frame. CONSTITUTION:A node 3A making continuous communication uses a reservation control circuit 36 to set a reservation bit in a header of an unreserved passing packet and reserves only the required packet number in one frame to start the continuous communication. A supervisory equipment 1 uses a frame generation circuit 12 to generate the control frame and uses a reservation control circuit 14 after the frame is sent to a transmission line to reserve entirely all slots in the next frame. Then the data stored in a transmission buffer 35 while the control frame is passing is sent in high speed by using the frame reserved entirely for the continuous communication. Thus, the data in the buffer 35 and a reception buffer 34 is kept to a proper quantity. That is, since the storage data in the buffer 35 is adjusted properly, the intermission of the synchronizing continuous communication is prevented.

公开(公告)号：JPS61187445A

公开(公告)日：1986-08-21

申请号：JP2651285

申请日：1985-02-15

Applicant: FUJITSU LTD

Inventor： TAZAKI TAKASHI ,  FUKUDA HARUKI ,  MATSUDA MASAHIRO ,  AWAZU TOMOHIKO

Abstract: PURPOSE:To transmit a retransmission packet in a short time with simple processing by using a reception busy field to inform the disabled reception of a sender communication controller when no packet is received because no idle reception buffer memory exists, allowing the sender communication controller receiving the notice to reset the reception busy field of the packet and transmit it as a transmission packet. CONSTITUTION:Even when a branching/insertion control section 7 identifies that a reception packet (a) is effective and addresses to the own device, if an unreceivable signal (c) is added, the section 7 sends the packet not received while setting the reception busy field BY as busy. The sender communication controller discriminates that the packet is a packet not received by a destination communication controller, resets the reception busy field BY and sends the packet to a transmission line from an output terminal 11 via selector 4 as it is.

公开(公告)号：JPS61133740A

公开(公告)日：1986-06-21

申请号：JP25471084

申请日：1984-12-01

Applicant: Fujitsu Ltd

Inventor： MATSUDA MASAHIRO ,  FUKUDA HARUKI ,  TAZAKI TAKASHI ,  AWAZU TOMOHIKO

Abstract: PURPOSE: To constitute inexpensively more a loop system with high reliability by controlling a switch means to turn off a sub-loop and hold the transmission line in a ring form when power intermission takes place on a node connected to the sub-loop in a junction body.
CONSTITUTION: A power supply 19 of a node 7 is subjected to on/off control by a power intermission forecast bit addition circuit 18. The circuit 18 turns on the power supply 19 when power is applied by a power operating switch 21. When the power is applied by the switch 21 and the circuit 18 outputs a power supply cutoff forecast signal informing the power interruption to a data insertion circuit 15 before the power supply 19 is turned off. Thus, the data insertion circuit 15describes a power interruption forecast signal on a frame header part. The circuit 18 turns off the power 19 after a power cutoff forecast signal is outputted and after switch control is executed at the junction box 3.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过控制开关装置来关闭子回路并将传输线保持在环形状中，以便在连接到连接处的子回路的节点上发生停电时，从而廉价地构成具有高可靠性的环路系统 身体。 构成：节点7的电源19由电力中断预测位加法电路18进行开/关控制。电路18在通过电源操作开关21供电时接通电源19.当电源 由开关21施加，并且电路18在电源19断开之前输出通知数据插入电路15的电源中断的电源切断预测信号。 因此，数据插入电路15描述帧头部分上的电源中断预测信号。 断电预报信号输出后，在接线盒3执行开关控制后，电路18关断电源19。