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    Vector operating processor
    77.
    发明专利
    Vector operating processor 失效
    矢量运算处理器

    公开(公告)号：JPS58181165A

    公开(公告)日：1983-10-22

    申请号：JP6256682

    申请日：1982-04-16

    Applicant: Hitachi Ltd

    Inventor： ABE SHIGEO ,  BANDOU TADAAKI ,  HIRASAWA KOUTAROU ,  IDE TOSHIYUKI

    IPC: G06F7/00 ,  G06F9/30 ,  G06F15/16 ,  G06F15/167 ,  G06F15/78 ,  G06F17/16

    CPC classification number: G06F9/30134 ,  G06F9/30112 ,  G06F15/8084

    Abstract: PURPOSE: To facilitate supporting an intermediate data processing, by providing a first-in first-out buffer and reading out an intermediate result required for the next subscript while an operated intermediate result is stored temporarily in a memory or the like.
    CONSTITUTION: Addresses of memory units 1200 and 1300 are designated by an address of an address operating unit 1100 of a vector operating processor to perform two read operations and one write operation simultaneously. A first-in first-out (FIFO) buffer 250 is provided for these units 1200 and 1300 and is controlled by input and output control signals WE and RE. The input form units 1200 and 1300, the buffer 250, etc. to pipeline multiplier 700 and adder 1000 is performed by putting required data onto input busses B1WB4 through gate groups G1WG6. The intermediate result required for the next subscript is read out while the intermediate result is stored temporarily in units 1200 and 1300, thus supporting the processing of the intermediate result.
    COPYRIGHT: (C)1983,JPO&Japio

    Abstract translation: 目的：为了便于支持中间数据处理，通过提供先进先出缓冲器并读出下一个下标所需的中间结果，同时将操作的中间结果临时存储在存储器等中。 构成：存储器单元1200和1300的地址由矢量操作处理器的地址操作单元1100的地址指定，以同时执行两个读操作和一个写操作。 为这些单元1200和1300提供先进先出（FIFO）缓冲器250，并由输入和输出控制信号WE和RE控制。 通过将所需数据通过栅极组G1-G6将所需数据放入输入总线B1-B4，执行输入形式单元1200和1300，缓冲器250等到流水线乘法器700和加法器1000。 在将中间结果暂时存储在单元1200和1300中时，读出下一个下标所需的中间结果，从而支持中间结果的处理。

    DATA PROCESSOR HANDLING INSTRUCTION OF UNFIXED LENGTH
    80.
    发明专利
    DATA PROCESSOR HANDLING INSTRUCTION OF UNFIXED LENGTH 失效

    公开(公告)号：JPS5844539A

    公开(公告)日：1983-03-15

    申请号：JP14110381

    申请日：1981-09-09

    Applicant: HITACHI LTD ,  HITACHI ENG CO LTD

    Inventor： FUKUNAGA YASUSHI ,  BANDOU TADAAKI ,  HIRAOKA YOSHINARI ,  HIRASAWA KOUTAROU ,  MATSUMOTO HIDEKAZU ,  IDE TOSHIYUKI ,  KATOU TAKESHI ,  NAKANISHI HIROAKI ,  KAWAKAMI TETSUYA

    IPC: G06F9/32 ,  G06F9/34

    Abstract: PURPOSE:To ensure the sharing of an operand designator to plural operands, by using the operand designator again in case the setting of the continuation information of the operand designator is detected. CONSTITUTION:A signal line 205 showing an operand end flag E, a signal line 205 showing the continuous bit S of an operand designator and a signal line 215 showing the byte number of the operand designator are fed to a detector 65 of decoding process byte number. The value of addition of a DP register 69 is delivered to a signal line 214 to show address of the next operand designator. In case the flag E is not 1 and the signal having the designator continuation information of 1 is given, 0 is delivered to the line 214 so that the register 69 has the value as it is. Thus the same operand designator is used also for the process of the next operand. As a result, the same operand is repetitively used.

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