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    BRANCH PREDICTING SYSTEM
    71.
    发明专利
    BRANCH PREDICTING SYSTEM 失效

    公开(公告)号：JPH03250221A

    公开(公告)日：1991-11-08

    申请号：JP4542490

    申请日：1990-02-28

    Applicant: HITACHI LTD

    Inventor： NAKAMIGAWA TETSUAKI ,  TANAKA SHIGEYA ,  KUROSAWA KENICHI ,  HOTTA TAKASHI ,  NAKATSUKA YASUHIRO ,  TAKEMOTO TAKESHI

    IPC: G06F9/38

    Abstract: PURPOSE:To improve the performance of calculation by defining the updating condition of a branch predicting table when the condition of a condition branching instruction is established and the branching destination is on the back of the instruction itself. CONSTITUTION:When the contents of an address branching instruction address (BIA) 1001 as a second instruction are coincident at time t2, an instruction address selector (IASEL) 105 sends the contents of a branching destination address (BTA) 1002 to an instruction address register (IAR) 106 as the address to be next read and in order to calculate the address to be next read, the contents are sent to an incrementer (INC) 104 as well. Further, for recovery in the case of failing prediction, the contents [(a)+4] of a program counter (PC) 103 are saved in a saving register (PCS) 108. In such a manner, reading is started from an predicted branching destination address (b) at time t3 and reading occurs from an address (b+4) at time t4. When the condition is established as the executed result of the second instruction at the time t4 and it is confirmed that branching occurs, the prediction is made successful. Thus, the condition branching is executed without useless waiting time and the performance of a computer is improved.

    METHOD AND DEVICE FOR DECIDING HOLDING/NON-HOLDING OF INTERIM RESULT AND RULE COMPILER AND RULE INTERPRETER CONTAINING THE DEVICE
    72.
    发明专利
    METHOD AND DEVICE FOR DECIDING HOLDING/NON-HOLDING OF INTERIM RESULT AND RULE COMPILER AND RULE INTERPRETER CONTAINING THE DEVICE 失效

    公开(公告)号：JPH03127228A

    公开(公告)日：1991-05-30

    申请号：JP26504889

    申请日：1989-10-13

    Applicant: HITACHI LTD

    Inventor： SHIMADA MASARU ,  KUROSAWA KENICHI ,  HIRAYAMA YOICHI ,  MORI SEIZO ,  NAKANO TOSHIHIKO

    IPC: G06F9/44 ,  G06N5/04

    Abstract: PURPOSE:To increase the inference processing speed by deciding a case where the interim result is held or a case where no interim result is held that has the smaller inference time before the inference is actually carried out. CONSTITUTION:A rule compiler 1 infers a rule program 100 described by a user and produces a rule machine word instruction. Then a case where the interim result is held and the inference is carried out by reference to the interim result or a case where the collation is directly carried out by no reference to the interim result that requires a smaller processed variable including the processing time, etc., is decided before a rule is carried out and the inference is actually performed. Then the actual inference is carried out based on the result of decision, that is, the interim result is held or not held. As a result, the useless interim result operations is omitted and the inference applying the execution of a rule is carried out at a high speed.

    METHOD FOR CONTROLLING BRANCH FORECASTING
    73.
    发明专利
    METHOD FOR CONTROLLING BRANCH FORECASTING 失效

    公开(公告)号：JPH01258030A

    公开(公告)日：1989-10-16

    申请号：JP8420288

    申请日：1988-04-07

    Applicant: HITACHI LTD

    Inventor： HIRAYAMA YOICHI ,  KUROSAWA KENICHI ,  BANDO TADAAKI ,  TAKATANI SOICHI

    IPC: G06F9/38

    Abstract: PURPOSE:To simplify hardware and to make branch instruction processing efficient by holding an instruction address generated physically immediately after an instruction in execution and comparing the held address with a practical branched address. CONSTITUTION:A next address physically continuously allocated next to an instruction being executed in an execution unit 120 is held in a next address register 130. The held contents are compared with a forecasting branched address in a branch forecasting table 150 or a practical branched address obtained from the unit 120 by comparators 170, 175. Even if condition branching information is not stored in respective stage of a pipe-line, branch forecasting can be controlled, so that hardware for condition branching information is not required. Since a failure in preceding branch when the branched address corresponds to a register can be detected by the comparators, branch forecasting for dynamically changing a branched address can be executed with a high hit ratio.

    PIPELINE TYPE DATA PROCESSOR
    74.
    发明专利
    PIPELINE TYPE DATA PROCESSOR 失效

    公开(公告)号：JPH01140234A

    公开(公告)日：1989-06-01

    申请号：JP29597187

    申请日：1987-11-26

    Applicant: HITACHI LTD

    Inventor： HIRAYAMA YOICHI ,  YAMAGUCHI SHINICHIRO ,  KUROSAWA KENICHI ,  BANDO TADAAKI ,  TAKATANI SOICHI

    IPC: G06F9/28 ,  G06F9/22

    Abstract: PURPOSE:To determine the action of the head microinstruction of a microprogram by setting the mode type of read/write to a state register by the designation of a microinstruction being executed. CONSTITUTION:A head address 2A from a decoding unit 210 is latched by a register 110 through an address generating part 100 when there is a termination signal 1A of the microprogram from a decoder 130. Next, by this address A, memories 115 and 120 are accessed and microinstructions 1D and 1E are read out. A selector 125 selects one of the instructions 1D and 1E by the termination signal 1A, a mode signal 2B, a flag signal 1C and a least significant bit signal 1F. The selected instruction 1D or 1E is sent to the decoding part 130, decoded and sent to an execution unit 225. When '1' is set to a state register 135 by a state setting signal 1B, the instruction 1E of a read mode is selected and when '0' is set to the register 135, the instruction 1D of a write mode is selected.

    CENTRAL PROCESSING UNIT
    76.
    发明专利
    CENTRAL PROCESSING UNIT 失效

    公开(公告)号：JPS63216134A

    公开(公告)日：1988-09-08

    申请号：JP4889287

    申请日：1987-03-05

    Applicant: HITACHI LTD ,  HITACHI PROCESS COMPUTER ENG

    Inventor： SUZUKI HIROSHI ,  KUROSAWA KENICHI

    IPC: G06F9/35 ,  G06F9/22 ,  G06F9/34

    Abstract: PURPOSE:To effectively store the result of arithmetic operation into a register when linking from a microprogram to the software by operating the register depending on the content of a memory. CONSTITUTION:A means 3 decoding an instruction form capable of indirectly instructing the register by using a memory address represented in a machine language instruction, generates a head address of the microprogram stored in a control storage 4 based on the instruction code of the machine language instruction. The microprogram is read one after another from the control storage 4 to control the hardware operation executing the machine language instruction. Identification means, 9, 10 are incorporated as a part of the microprogram and when a register number exists in the memory address represented by the operand of the instruction, the data read from the memory is accessed to the register file 7. Thus, the access to the register in transferring the machine language instruction from the microprogram is attained efficiently.

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