公开(公告)号：GB2495362B

公开(公告)日：2013-11-06

申请号：GB201213322

申请日：2012-07-26

Applicant: IBM

Inventor： SALAPURA VALENTINA ,  GSCHWIND MICHAEL KARL

IPC: G06F9/38 ,  G06F9/30

公开(公告)号：GB2495360B

公开(公告)日：2013-08-28

申请号：GB201213316

申请日：2012-07-26

Applicant: IBM

Inventor： GSCHWIND MICHAEL KARL ,  SALAPURA VALENTINA

IPC: G06F9/30

公开(公告)号：GB2495361A8

公开(公告)日：2013-04-24

申请号：GB201213318

申请日：2012-07-26

Applicant: IBM

Inventor： GSCHWIND MICHAEL KARL ,  SALAPURA VALENTINA

IPC: G06F9/30 ,  G06F9/38

Abstract: A multi-level register hierarchy is disclosed comprising a first level pool of registers for caching registers of a second level pool of registers in a system wherein programs can dynamically release and re-enable architected registers such that released architected registers need not be maintained by the processor, the processor accessing operands from the first level pool of registers, wherein a last-use instruction is identified as having a last use of an architected register before being released, the last-use architected register being released causes the multi-level register hierarchy to discard any correspondence of an entry to said last use architected register.

公开(公告)号：GB2495360A8

公开(公告)日：2013-04-24

申请号：GB201213316

申请日：2012-07-26

Applicant: IBM

Inventor： GSCHWIND MICHAEL KARL ,  SALAPURA VALENTINA

IPC: G06F9/30

公开(公告)号：GB2495361A

公开(公告)日：2013-04-10

申请号：GB201213318

申请日：2012-07-26

Applicant: IBM

Inventor： GSCHWIND MICHAEL KARL ,  SALAPURA VALENTINA

IPC: G06F9/30 ,  G06F9/38

Abstract: A multi-level register hierarchy comprises a first level pool of registers 507 for caching registers of a second level pool of registers 506 in a system wherein programs can dynamically release and re-enable architected registers such that released architected registers need not be maintained by the processor, the processor accessing operands through the first level pool of registers. The registers are assigned to each pool by associating with an entry 502 in one of the register pools. Where a last-use instruction is identified as having a last use of an architected register, that register is unassigned from both first and second level pools once the instruction is executed, allowing the entry to be reassigned to another register. The first level pool may hold recently accessed, or frequently accessed, registers.

公开(公告)号：DE102012216592A1

公开(公告)日：2013-04-04

申请号：DE102012216592

申请日：2012-09-18

Applicant: IBM

Inventor： GSCHWIND MICHAEL K ,  SALAPURA VALENTINA

IPC: G06F9/30

Abstract: Eine Präfixanweisung wird ausgeführt und leitet Operanden an eine nächste Anweisung weiter, ohne die Operanden in einer architekturdefinierten Ressource zu speichern, so dass die Ausführung der nächsten Anweisung die von der Präfixanweisung bereitgestellten Operanden verwendet, um eine Operation durchzuführen, wobei die Operanden ein Direktfeld der Präfixanweisung oder ein Zielregister der Ausführung der Präfixanweisung sein können.