公开(公告)号：US20180240868A1

公开(公告)日：2018-08-23

申请号：US15902158

申请日：2018-02-22

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Ralf Rudolf

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/74 ,  H01L21/761 ,  H01L21/265

CPC classification number: H01L29/0623 ,  H01L21/26513 ,  H01L21/743 ,  H01L21/761 ,  H01L21/763 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/1087

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is on the semiconductor substrate. A buried semiconductor layer of the second conductivity type is on the first semiconductor layer. A second semiconductor layer of the second conductivity type is on the buried semiconductor layer. A trench extends through each of the second semiconductor layer, the buried semiconductor layer, and the first semiconductor layer, and into the semiconductor substrate. An insulating structure lines walls of the trench. A conductive filling in the trench is electrically coupled to the semiconductor substrate at a bottom of the trench.

公开(公告)号：US09985126B2

公开(公告)日：2018-05-29

申请号：US15060790

申请日：2016-03-04

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.

公开(公告)号：US09917163B2

公开(公告)日：2018-03-13

申请号：US15437932

申请日：2017-02-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L27/15 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4175 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/156 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7835

Abstract: A semiconductor device comprises a field effect transistor in a semiconductor substrate having a first main surface. The field effect transistor comprises a source region, a drain region, a body region, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region, and the gate electrode is disposed in gate trenches. The body region is disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a ridge extending along the first direction, the body region being adjacent to the source region and the drain region. The semiconductor device further comprises a source contact and a body contact, the source contact being electrically connected to a source terminal, the body contact being electrically connected to the source contact and to the body region.

公开(公告)号：US09806188B2

公开(公告)日：2017-10-31

申请号：US15173337

申请日：2016-06-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Markus Zundel

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L21/768 ,  H01L21/28 ,  H01L23/48 ,  H01L21/74 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/28008 ,  H01L21/28229 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.

公开(公告)号：US09799762B2

公开(公告)日：2017-10-24

申请号：US13692059

申请日：2012-12-03

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

Abstract: A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone.

公开(公告)号：US20170257025A1

公开(公告)日：2017-09-07

申请号：US15060737

申请日：2016-03-04

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Steffen Thiele

IPC: H02M3/156 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06

CPC classification number: H02M3/156 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7825 ,  H01L29/7831 ,  H02M3/155

Abstract: A switched-mode power converter includes an inductive storage element and a cascode circuit. The cascode circuit includes a double-gate field effect transistor. A switchable load path of the double-gate field effect transistor is electrically connected in series with the inductive storage element.

公开(公告)号：US20170256641A1

公开(公告)日：2017-09-07

申请号：US15060790

申请日：2016-03-04

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.

公开(公告)号：US09735243B2

公开(公告)日：2017-08-15

申请号：US14082491

申请日：2013-11-18

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Rolf Weis ,  Franz Hirler ,  Martin Vielemeyer ,  Markus Zundel ,  Peter Irsigler

IPC: H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/4175 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7826 ,  H01L29/7835

Abstract: A semiconductor device comprises a transistor formed in a semiconductor body having a first main surface. The transistor comprises a source region, a drain region, a channel region, a drift zone, a source contact electrically connected to the source region, a drain contact electrically connected to the drain region, and a gate electrode at the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction. One of the source contact and the drain contact is adjacent to the first main surface, the other one of the source contact and the drain contact is adjacent to a second main surface that is opposite to the first main surface.

公开(公告)号：US09705026B2

公开(公告)日：2017-07-11

申请号：US15009271

申请日：2016-01-28

Applicant: Infineon Technologies AG

Inventor： Joost Willemen ,  Michael Mayerhofer ,  Ulrich Glaser ,  Yiqun Cao ,  Andreas Meiser ,  Magnus-Maria Hell ,  Matthias Stecher ,  Julien Lebon

IPC: H01L21/00 ,  H01L31/173 ,  H01L27/02 ,  H01L27/06 ,  H01L27/15 ,  H01L29/808 ,  H02H3/20

CPC classification number: H01L31/173 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/15 ,  H01L29/808 ,  H02H3/20

Abstract: A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

公开(公告)号：US20160300944A1

公开(公告)日：2016-10-13

申请号：US15187889

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Till Schloesser ,  Franz Hirler

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/8083

Abstract: A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The second sidewall faces the first sidewall via the channel region. The channel separation trench is filled with an insulating separation trench filling consisting of an insulating material in direct contact with the channel region. The source region and the drain region are disposed along a first direction. The first direction is parallel to the main surface.

Abstract translation: 半导体器件包括形成在具有主表面的半导体衬底中的晶体管。 晶体管包括第一导电类型的源极区域，第一导电类型的漏极区域，第二导电类型的沟道区域，与沟道区域的第一侧壁相邻的栅极沟槽，设置在该沟道区域中的栅极导电材料 栅极沟槽，栅极导电材料连接到栅极端子以及与沟道区域的第二侧壁相邻的沟道分离沟槽。 第二侧壁经由通道区域面向第一侧壁。 通道分离沟槽填充有由与沟道区直接接触的绝缘材料构成的绝缘分离沟槽填充物。 源极区域和漏极区域沿着第一方向设置。 第一个方向平行于主表面。