公开(公告)号：US12150297B2

公开(公告)日：2024-11-19

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Arnab Sen Gupta ,  Matthew V. Metz ,  Elliot N. Tan ,  Hui Jae Yoo ,  Travis W. Lajoie ,  Van H. Le ,  Pei-Hua Wang

IPC: H10B12/00 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：US12080605B2

公开(公告)日：2024-09-03

申请号：US17866122

申请日：2022-07-15

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard E. Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick R. Morrow ,  Jeffrey D. Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/53295 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/785

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US11769814B2

公开(公告)日：2023-09-26

申请号：US16455659

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Kevin L. Lin ,  Tristan Tronic

IPC: H01L29/51 ,  H01L29/66

CPC classification number: H01L29/515 ,  H01L29/6653

Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.

公开(公告)号：US11764104B2

公开(公告)日：2023-09-19

申请号：US16454553

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Ehren Mannebach ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Hui Jae Yoo

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76264 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/266 ,  H01L21/26533 ,  H01L21/31111 ,  H01L21/76267 ,  H01L29/0649 ,  H01L29/7853

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US11640961B2

公开(公告)日：2023-05-02

申请号：US16954126

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Aaron D. Lilak ,  Willy Rachmady ,  Rishabh Mehandru ,  Kimin Jun ,  Anh Phan ,  Hui Jae Yoo ,  Patrick Morrow ,  Cheng-Ying Huang ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20230092244A1

公开(公告)日：2023-03-23

申请号：US17481760

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Hui Jae Yoo ,  Van H. Le ,  Sarah Atanasov ,  Abhishek A. Sharma

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: Described herein are back-gated transistors with fin-shaped gates, and IC devices including such transistors. The transistor includes a gate electrode formed over a support structure, where the gate electrode includes a metal fin that extends perpendicular to the support structure. A gate dielectric formed of a metal oxide film is deposited over the gate electrode and conforming to the fin shape, and a channel material formed of a high mobility oxide semiconductor film is deposited over the gate dielectric, the channel material also conforming to the fin shape. Source and drain contacts may be arranged so that the fin creates a channel with a larger channel width or a longer channel length.

公开(公告)号：US20230081882A1

公开(公告)日：2023-03-16

申请号：US17474689

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Abhishek A. Sharma ,  Aaron D. Lilak ,  Hui Jae Yoo ,  Scott B. Clendenning ,  Van H. Le ,  Tristan A. Tronic ,  Urusa Alaan

IPC: H01L27/108 ,  H01L27/06 ,  G11C5/10

Abstract: A memory structure includes a spacer between a first side of a wordline conductor and a bitline conductor. A semiconductor material has horizontal portions extending from the bitline conductor along a top and bottom of the wordline conductor and has a contact portion extending along a second side of the wordline conductor between and connecting the horizontal portions. A high-κ dielectric is between the semiconductor material and the wordline conductor. A capacitor has a first conductor, a second conductor, and an insulator between the first and second conductors, where the first conductor contacts the contact portion of the semiconductor material along the first side of the wordline conductor, and the second conductor connects to a ground terminal.

公开(公告)号：US20230064541A1

公开(公告)日：2023-03-02

申请号：US17462058

申请日：2021-08-31

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Kimin Jun ,  Wilfred Gomes ,  Hui Jae Yoo

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.

公开(公告)号：US20230056640A1

公开(公告)日：2023-02-23

申请号：US17406558

申请日：2021-08-19

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Clifford Lu Ong ,  Van H. Le ,  Hui Jae Yoo

IPC: H01L23/48 ,  H01L25/065 ,  G11C11/412 ,  G11C11/418 ,  G11C11/408

Abstract: Described herein are stacked memory devices that include some peripheral devices for controlling the memory in a separate layer from one or more memory arrays. The layers of the memory device are connected together using vias, which transfer power and data between the layers. In some examples, a portion of the peripheral devices are included in a memory layer, and another portion are included in a peripheral device layer. Multiple layers of memory arrays and/or peripheral devices may be included, e.g., one peripheral device layer may control multiple layers of memory arrays, or different layers of memory arrays may have dedicated peripheral device layers. Different types of memory arrays, such as DRAM or SRAM, may be included.

公开(公告)号：US11587827B2

公开(公告)日：2023-02-21

申请号：US17567762

申请日：2022-01-03

Applicant: Intel Corporation

Inventor： Sean King ,  Hui Jae Yoo ,  Sreenivas Kosaraju ,  Timothy Glassman

IPC: H01L21/76 ,  H01L23/52 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.