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    Non-volatile memory express over fabric (NVMeOF) using volume management device
    71.
    发明授权
    Non-volatile memory express over fabric (NVMeOF) using volume management device 有权

    公开(公告)号：US10958729B2

    公开(公告)日：2021-03-23

    申请号：US15599020

    申请日：2017-05-18

    Applicant: Intel Corporation

    Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

    IPC: H04L29/08 ,  G06F3/06 ,  G06F9/455 ,  H04L12/24 ,  H04L29/06

    Abstract: Non-volatile Memory Express over Fabric (NVMeOF) using Volume Management Device (VMD) schemes and associated methods, systems and software. The schemes are implemented in a data center environment including compute resources in compute drawers and storage resources residing in pooled storage drawers that are communicatively couple via a fabric. Compute resources are composed as compute nodes or virtual machines/containers running on compute nodes to utilize remote storage devices in pooled storage drawers, while exposing the remote storage devices as local NVMe storage devices to software running on the compute nodes. This is facilitated by virtualizing the system's storage infrastructure through use of hardware-based components, firmware-based components, or a combination of hardware/firmware- and software-based components. The schemes support the use of remote NVMe storage devices using an NVMeOF protocol and/or use of non-NVMe storage devices using NVMe emulation.

    NETWORKED SHUFFLE STORAGE
    74.
    发明申请
    NETWORKED SHUFFLE STORAGE 审中-公开

    公开(公告)号：US20200210114A1

    公开(公告)日：2020-07-02

    申请号：US16634436

    申请日：2017-08-16

    Applicant: Intel Corporation

    Inventor： Xiao Hu ,  Huan Zhou ,  Sujoy Sen ,  Anjaneya R. Chagam Reddy ,  Mohan J. Kumar ,  Chong Han

    IPC: G06F3/06 ,  G06F16/23

    Abstract: Apparatuses for computing are disclosed herein. An apparatus may include a set of data reduction modules to perform data reduction operations on sets of (key, value) data pairs to reduce an amount of values associated with a shared key, wherein the (key, value) data pairs are stored in a plurality of queues located in a plurality of solid state drives remote from the apparatus. The apparatus may further include a memory access module, communicably coupled to the set of data reduction modules, to directly transfer individual ones of the sets of queued (key, value) data pairs from the plurality of remote solid state drives through remote random access of the solid state drives, via a network, without using intermediate staging storage. Other embodiments may be disclosed or claimed.

    Out-of-band management of FPGA bitstreams
    78.
    发明申请
    Out-of-band management of FPGA bitstreams 审中-公开

    公开(公告)号：US20190173734A1

    公开(公告)日：2019-06-06

    申请号：US15829935

    申请日：2017-12-03

    Applicant: Intel Corporation

    Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

    IPC: H04L12/24 ,  G06F15/78 ,  G06F17/50

    Abstract: Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.

    MECHANISMS FOR FPGA CHAINING AND UNIFIED FPGA VIEWS TO COMPOSED SYSTEM HOSTS
    79.
    发明申请
    MECHANISMS FOR FPGA CHAINING AND UNIFIED FPGA VIEWS TO COMPOSED SYSTEM HOSTS 审中-公开

    公开(公告)号：US20190171601A1

    公开(公告)日：2019-06-06

    申请号：US15829937

    申请日：2017-12-03

    Applicant: Intel Corporation

    Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

    IPC: G06F13/40 ,  G06F9/455

    Abstract: Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.

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