公开(公告)号：US09715397B2

公开(公告)日：2017-07-25

申请号：US14947321

申请日：2015-11-20

Applicant: INTEL CORPORATION

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F9/445 ,  G06F9/50 ,  G06F12/0891 ,  G06F1/10

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US09639762B2

公开(公告)日：2017-05-02

申请号：US14477595

申请日：2014-09-04

Applicant: Intel Corporation

Inventor： Shayok Chakraborty ,  Omesh Tickoo ,  Ravishankar Iyer

IPC: G06K9/00 ,  G11B20/10 ,  G11B27/30 ,  G06K9/62

CPC classification number: G06K9/00751 ,  G06K9/6271 ,  G06K2209/27 ,  G11B20/10527 ,  G11B27/30 ,  G11B2020/10537 ,  H04N21/41407 ,  H04N21/4223 ,  H04N21/44008 ,  H04N21/8456 ,  H04N21/8549

Abstract: System, apparatus, method, and computer readable media for on-the-fly captured video summarization. A video stream is incrementally summarized in concurrence with generation of the stream by a camera module. Saliency of the video stream summary is maintained as the stream evolves by updating the summary to include only the most significant frames. In one exemplary embodiment, saliency is determined by optimizing an objective function including terms that are indicative of both the diversity of a selection, and how representative the selection is to the processed portion of the video data corpus. A device platform including a CM and comporting with the exemplary architecture may provide video camera functionality at ultra-low power, and/or with ultra-low storage resources, and/or with ultra-low communication channel bandwidth.

公开(公告)号：US09535860B2

公开(公告)日：2017-01-03

申请号：US13743795

申请日：2013-01-17

Applicant: Intel Corporation

Inventor： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Jose S. Niell ,  Debra Bernstein ,  Deepak Limaye ,  Ioannis T. Schoinas ,  Ravishankar Iyer

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1663 ,  G06F13/1605 ,  G06F13/161 ,  G06F2212/1024 ,  G06F2213/0064 ,  Y02D10/14

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。

公开(公告)号：US09235256B2

公开(公告)日：2016-01-12

申请号：US14227680

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US08924748B2

公开(公告)日：2014-12-30

申请号：US14141992

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US20140223145A1

公开(公告)日：2014-08-07

申请号：US13992797

申请日：2011-12-30

Applicant: INTEL CORPORATION

Inventor： Srihari Makineni ,  Steven R. King ,  Zhen Fang ,  Alexander Redkin ,  Ravishankar Iyer ,  Pavel S. Smirnov ,  Dmitry Gusev ,  Dmitri Pavlov ,  May Wu

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F1/32 ,  G06F9/30196 ,  G06F9/3822 ,  G06F9/3891

Abstract: A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant.

Abstract translation: 处理器可以用仅执行需要完全向后兼容的一些部分指令集的核来构建。 因此，在一些实施例中，可以通过提供仅执行特定指令而不是其他指令的部分核来降低功耗。 不支持的指令可以以其他更节能的方式处理，使得包括部分核心的整体处理器可以完全向后兼容。

公开(公告)号：US08762599B2

公开(公告)日：2014-06-24

申请号：US13729172

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Michael J. Espig ,  Zhen Fang ,  Ravishankar Iyer ,  David J. Harriman

IPC: G06F3/00

CPC classification number: G06F13/24 ,  G06F9/542

Abstract: In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于处理从主机处理器接收的注册消息的方法，其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。 来自消息的信息可以存储在轮询表中，并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。 描述和要求保护其他实施例。