公开(公告)号：US11816036B2

公开(公告)日：2023-11-14

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

CPC classification number: G06F12/0868 ,  G06F3/065 ,  G06F3/068 ,  G06F3/0619 ,  G06F12/0811 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/311 ,  G06F2212/6046

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US11486719B2

公开(公告)日：2022-11-01

申请号：US16941163

申请日：2020-07-28

Applicant: Intel Corporation

Inventor： Ren Wang ,  Zhonghong Ou ,  Arvind Kumar ,  Kristoffer Fleming ,  Tsung-Yuan C. Tai ,  Timothy J. Gresham ,  John C. Weast ,  Corey Kukis

IPC: G01C21/34 ,  H04W4/024 ,  H04W4/029 ,  H04B17/318 ,  H04W24/08

Abstract: Examples disclosed herein include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data.

公开(公告)号：US20220261351A1

公开(公告)日：2022-08-18

申请号：US17738919

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US20210141676A1

公开(公告)日：2021-05-13

申请号：US17152573

申请日：2021-01-19

Applicant: Intel Corporation

Inventor： Ren Wang ,  Daniel P. Daly ,  Antoine Kaufmann ,  Saikrishna Edupuganti ,  Tsung-Yuan C. Tai

IPC: G06F9/50

Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.

公开(公告)号：US11005884B2

公开(公告)日：2021-05-11

申请号：US15720821

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sameh Gobriel ,  Christian Maciocco ,  Byron Marohn ,  Ren Wang ,  Tsung-Yuan C. Tai

IPC: H04L29/06 ,  H04L9/32 ,  G06F21/55 ,  G06F16/22

Abstract: A computing apparatus for providing a node within a distributed network function, including: a hardware platform; a network interface to communicatively couple to at least one other peer node of the distributed network function; a distributor function including logic to operate on the hardware platform, including a hashing module configured to receive an incoming network packet via the network interface and perform on the incoming network packet a first-level hash of a two-level hash, the first level hash being a lightweight hash with respect to a second-level hash, the first level hash to deterministically direct a packet to one of the nodes of the distributed network function as a directed packet; and a denial of service (DoS) mitigation engine to receive notification of a DoS attack, identify a DoS packet via the first-level hash, and prevent the DoS packet from reaching the second-level hash.

公开(公告)号：US20210049102A1

公开(公告)日：2021-02-18

申请号：US16834845

申请日：2020-03-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10805418B2

公开(公告)日：2020-10-13

申请号：US16511855

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Vallabhajosyula S. Somayazulu ,  Eve M. Schooler ,  Hassnaa Moustafa ,  Andrew Stephen Brown ,  Rath Vannithamby ,  Srikathyayani Srikanteswara ,  David John Zage ,  Ren Wang ,  Christian Maciocco ,  David E. Ott ,  Jeffrey Christopher Sedayao ,  David E. Cohen ,  Sung Lee

IPC: H04L29/08 ,  H04L12/26 ,  G06F16/23 ,  H04L12/24 ,  G06F16/957 ,  H04L29/06 ,  H04L12/841 ,  H04L12/773 ,  H04L12/741 ,  H04L12/813 ,  H04L29/12 ,  H04L12/721 ,  H04L12/911 ,  H04L12/715

Abstract: Generally discussed herein are systems, devices, and methods for managing content of an information centric network (ICN). A component of an ICN can include a memory including an extended content store that includes content from at least one other component of the ICN, and first attributes of the content, the first attributes including a content popularity value that indicates a number of requests for the content, and processing circuitry to increment the content popularity value in response to a transmission of a first content packet that includes the content, the first content packet transmitted in response to receiving an interest packet.

公开(公告)号：US20200218631A1

公开(公告)日：2020-07-09

申请号：US16827410

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Ren Wang ,  Bin Li ,  Andrew J. Herdrich ,  Tsung-Yuan C. Tai ,  Ramakrishna Huggahalli

IPC: G06F11/34 ,  G06F12/0811 ,  G06F12/121 ,  G06F13/16 ,  G06F11/30 ,  G06F13/42 ,  G06F12/128 ,  G06F12/084 ,  G06F12/0888

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.

公开(公告)号：US20200042479A1

公开(公告)日：2020-02-06

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F12/0811 ,  G06F13/16 ,  G06F9/54 ,  G06F12/0868

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20190303303A1

公开(公告)日：2019-10-03

申请号：US15940719

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Venkata Krishnan ,  Lawrence Stewart ,  Anil Vasudevan ,  Ren Wang

IPC: G06F12/123 ,  G06F12/122 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0811

Abstract: A method for detecting repetitive data accesses and automatically storing the data into the local cache, the method including: storing a cache line in a first cache of a first processor; tracking accesses to the cache line by monitoring executions of a snapshot instruction made by a second processor; and controlling enablement of a load operation based on the tracked accesses. The load operation is performed by storing a copy of the cache line into a local cache of the second processor and changing the cache coherence state of the cache line in the first cache to a shared state.