公开(公告)号：US11640984B2

公开(公告)日：2023-05-02

申请号：US16363952

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Chia-Ching Lin ,  Owen Loh ,  Seung Hoon Sung ,  Aditya Kasukurti ,  Sou-Chi Chang ,  Tanay Gosavi ,  Ashish Verma Penumatcha

IPC: H01L29/51 ,  H01L29/78

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

公开(公告)号：US20220415818A1

公开(公告)日：2022-12-29

申请号：US17358962

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Jasmeet Chawla ,  Matthew Metz ,  Sean King ,  Ramanan Chebiam ,  Mauro Kobrinsky ,  Scott Clendenning ,  Sudarat Lee ,  Christopher Jezewski ,  Sunny Chugh ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768

Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

公开(公告)号：US20220352068A1

公开(公告)日：2022-11-03

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11444024B2

公开(公告)日：2022-09-13

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11335793B2

公开(公告)日：2022-05-17

申请号：US16957667

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20210036023A1

公开(公告)日：2021-02-04

申请号：US16529643

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Jack Kavalieros ,  Anand Murthy ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Cheng-Ying Huang ,  Cory Bomberger

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66

Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.

公开(公告)号：US20200098757A1

公开(公告)日：2020-03-26

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US20190189753A1

公开(公告)日：2019-06-20

申请号：US16326663

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Matthew Metz ,  Gilbert Dewey ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Sean T. Ma ,  Willy Rachmady

IPC: H01L29/12 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/122 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/20

Abstract: Semiconductor devices, computing devices, and related methods are disclosed herein. A semiconductor device includes a seed material, an epitaxial material in contact with the seed material, and at least one quantum region including an elastic stiffness that is greater than an elastic stiffness of the epitaxial material. The epitaxial material has lattice parameters that are different from lattice parameters of the seed material by at least a threshold amount. Lattice parameters of the quantum region are within the threshold amount of the lattice parameters of the epitaxial material. A method includes disposing an epitaxial material on a seed material, disposing a quantum region on the epitaxial material, and disposing the epitaxial material on the quantum region.

公开(公告)号：US10263074B2

公开(公告)日：2019-04-16

申请号：US15605795

申请日：2017-05-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20

Abstract: Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US10121897B2

公开(公告)日：2018-11-06

申请号：US15660574

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/267 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08 ,  H01L29/201 ,  H01L29/207 ,  H01L29/417 ,  H01L29/45 ,  H01L29/16

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.