公开(公告)号：US20180150334A1

公开(公告)日：2018-05-31

申请号：US15719770

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Joe Grecco ,  Henry MItchel ,  Rahul Khanna ,  Slawomir Putyrski ,  Sujoy Sen ,  Paul Dormitzer

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for providing accelerated functions as a service in a disaggregated architecture include a compute device that is to receive a request for an accelerated task. The task is associated with a kernel usable by an accelerator sled communicatively coupled to the compute device to execute the task. The compute device is further to determine, in response to the request and with a database indicative of kernels and associated accelerator sleds, an accelerator sled that includes an accelerator device configured with the kernel associated with the request. Additionally, the compute device is to assign the task to the determined accelerator sled for execution. Other embodiments are also described and claimed

公开(公告)号：US09485178B2

公开(公告)日：2016-11-01

申请号：US14229545

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Srihari Makikeni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/931

CPC classification number: H04L45/74 ,  H04L49/20 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166

Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

公开(公告)号：US09276854B2

公开(公告)日：2016-03-01

申请号：US14564705

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Linden Cornett ,  Parthasarathy Sarangam ,  Sujoy Sen

IPC: H04L12/28 ,  H04L12/743 ,  H04L12/54 ,  H04L12/801 ,  H04L12/803 ,  H04L12/815 ,  H04L12/863 ,  H04L12/755

CPC classification number: H04L45/7453 ,  H04L45/021 ,  H04L47/10 ,  H04L47/125 ,  H04L47/13 ,  H04L47/22 ,  H04L47/50 ,  H04L47/621 ,  H04L47/6225 ,  H04L47/6295

Abstract: In an embodiment, a method is provided. The method of this embodiment provides generating one or more packets of data, the one or more packets of data being associated with a connection; and associating the one or more packets with one of a plurality of transmit queues based, at least in part, on the connection associated with the one or more packets.

公开(公告)号：US12260263B2

公开(公告)日：2025-03-25

申请号：US17528374

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a graphics processing unit (GPU) to: provide a virtual GPU monitor (VGM) to interface over a network with a middleware layer of a client platform, the VGM to interface with the middleware layer using a message passing interface; configure and expose, by the VGM, virtual functions (VFs) of the GPU to the middleware layer of the client platform; intercept, by the VGM, request messages directed to the GPU from the middleware layer, the request messages corresponding to VFs of the GPU to be utilized by the client platform; and generate, by the VGM, a response to the request messages for the middleware client.

公开(公告)号：US12192024B2

公开(公告)日：2025-01-07

申请号：US17103711

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Bassam N. Coury ,  Sujoy Sen ,  Thomas E. Willis ,  Durgesh Srivastava

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

Abstract: Examples described herein includes a network interface controller comprising a memory interface and a network interface, the network interface controller configurable to provide access to local memory and remote memory to a requester, wherein the network interface controller is configured with an amount of memory of different memory access speeds for allocation to one or more requesters. In some examples, the network interface controller is to grant or deny a memory allocation request from a requester based on a configuration of an amount of memory for different memory access speeds for allocation to the requester. In some examples, the network interface controller is to grant or deny a memory access request from a requester based on a configuration of memory allocated to the requester. In some examples, the network interface controller is to regulate quality of service of memory access requests from requesters.

公开(公告)号：US12192023B2

公开(公告)日：2025-01-07

申请号：US17103602

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

Abstract: Examples described herein and includes at least one processor and a direct memory access (DMA) device. In some examples, the DMA device is to: access a command from a memory region allocated to receive commands for execution by the DMA device, wherein the command is to access content from a local memory device or remote memory node. In some examples, the DMA device is to: determine if the content is stored in a local memory device or a remote memory node based on a configuration that indicates whether a source address refers to a memory address associated with the local memory device or the remote memory node and whether a destination address refers to a memory address associated with the local memory device or the remote memory node. In some examples, the DMA device is to: copy the content from a local memory device or copy the content to the local memory device using a memory interface.

公开(公告)号：US12191987B2

公开(公告)日：2025-01-07

申请号：US18388461

申请日：2023-11-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Rahul Khanna ,  Sujoy Sen ,  Karthik Kumar

IPC: H04L43/08 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06F15/16 ,  G06F16/174 ,  G06F16/901 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04B10/25 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14 ,  B25J15/00 ,  B65G1/04 ,  G05D23/19 ,  G05D23/20 ,  G06F9/50 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F13/42 ,  G06F15/80 ,  G06Q10/06 ,  G06Q10/0631 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/00 ,  G11C5/06 ,  H04J14/00 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/28 ,  H04L41/02 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/38 ,  H04L47/70 ,  H04L47/765 ,  H04L47/78 ,  H04L47/80 ,  H04L47/83 ,  H04L49/15 ,  H04L49/55 ,  H04L61/00 ,  H04L67/00 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/51 ,  H04Q1/04 ,  H04W4/02 ,  H04W4/80 ,  H05K1/02 ,  H05K1/18 ,  H05K5/02 ,  H05K7/20 ,  H05K13/04

Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

公开(公告)号：US12132581B2

公开(公告)日：2024-10-29

申请号：US17103802

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Sujoy Sen ,  Durgesh Srivastava ,  Thomas E. Willis ,  Bassam N. Coury ,  Marcelo Cintra

IPC: H04L12/18 ,  G06F12/02 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  H04L12/54 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  H04L12/70

CPC classification number: H04L12/1868 ,  G06F12/0238 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/4059 ,  H04L12/5601 ,  H04L45/74 ,  H04L49/201 ,  H04L67/1095 ,  G06F2213/28 ,  H04L2012/562

Abstract: Examples described herein includes an apparatus comprising: a network interface configured to: receive a request to copy data from a local memory to a remote memory; based on a configuration that the network interface is to manage a cache store the data into the cache and record that the data is stored in the cache. In some examples, store the data in the cache comprises store most recently evicted data from the local memory into the cache. In some examples, the network interface is to store data evicted from the local memory that is not stored into the cache into one or more remote memories.

公开(公告)号：US12093748B2

公开(公告)日：2024-09-17

申请号：US17133066

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Reshma Lal ,  Pradeep Pappachan ,  Luis Kida ,  Soham Jayesh Desai ,  Sujoy Sen ,  Selvakumar Panneer ,  Robert Sharp

IPC: G06F9/50 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/5083 ,  G06F9/3814 ,  G06F9/5027 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes one or more processors to facilitate receiving a manifest corresponding to graph nodes representing regions of memory of a remote client machine, the graph nodes corresponding to a command buffer and to associated data structures and kernels of the command buffer used to initialize a hardware accelerator and execute the kernels, and the manifest indicating a destination memory location of each of the graph nodes and dependencies of each of the graph nodes; identifying, based on the manifest, the command buffer and the associated data structures to copy to the host memory; identifying, based on the manifest, the kernels to copy to local memory of the hardware accelerator; and patching addresses in the command buffer copied to the host memory with updated addresses of corresponding locations in the host memory.

公开(公告)号：US20240143410A1

公开(公告)日：2024-05-02

申请号：US18405679

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Francesc Guim Bernat ,  Slawomir Putyrski ,  Joe Grecco ,  Henry Mitchel ,  Evan Custodio ,  Rahul Khanna ,  Sujoy Sen

IPC: G06F9/50 ,  G06F3/06 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/455 ,  G06F9/48 ,  G06F9/54 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16 ,  G06F16/174 ,  G06F21/57 ,  G06F21/62 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  H01R13/453 ,  H01R13/631 ,  H03K19/173 ,  H03M7/30 ,  H03M7/40 ,  H03M7/42 ,  H04L9/08 ,  H04L12/28 ,  H04L12/46 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/14

CPC classification number: G06F9/505 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0641 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/45533 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5005 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/5083 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3079 ,  G06F11/3409 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/453 ,  H01R13/4536 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/12 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L49/104 ,  H04L61/5007 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/63 ,  H04L67/75 ,  H05K7/1452 ,  H05K7/1487 ,  H05K7/1491 ,  H04L47/78

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.