中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

154 records (took 0.041 seconds)

    MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS
    74.
    发明公开
    MEMORY PROGRAMMING USING CONSECUTIVE COARSE-FINE PROGRAMMING OPERATIONS OF THRESHOLD VOLTAGE DISTRIBUTIONS 审中-公开

    公开(公告)号：US20230360705A1

    公开(公告)日：2023-11-09

    申请号：US18138551

    申请日：2023-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Huai-Yuan Tseng ,  Giovanni Maria Paolucci ,  Kishore Kumar Muchherla ,  James Fitzpatrick ,  Akira Goda

    IPC: G11C16/12 ,  G11C16/08

    CPC classification number: G11C16/12 ,  G11C16/08

    Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

    DATA REORDERING AT A MEMORY SUBSYSTEM
    76.
    发明公开
    DATA REORDERING AT A MEMORY SUBSYSTEM 审中-公开

    公开(公告)号：US20230333770A1

    公开(公告)日：2023-10-19

    申请号：US17723244

    申请日：2022-04-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Karl David Schuh ,  Kishore Kumar Muchherla ,  Daniel Jerre Hubbard ,  James Fitzpatrick

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A set of host data items is received for programming to the memory subsystem. The set of host data items is programmed to a first region of the memory subsystem that includes one or more memory devices. A determination is made that a sequence at which the set of host data items are programmed across memory devices of the first region does not correspond to a target sequence associated with accessing the set of host data items via the first region. The target sequence corresponds to a sequence that enables a host data items programmed to the memory sub-system to be accessed in parallel. The set of host data items is copied from the first region to a second region of the memory subsystem. A sequence at which the set of host data items is copied to memory devices of the second region corresponds to the target sequence.

    Double interleaved programming of a memory device in a memory sub-system
    78.
    发明授权
    Double interleaved programming of a memory device in a memory sub-system 有权

    公开(公告)号：US11699491B2

    公开(公告)日：2023-07-11

    申请号：US17247643

    申请日：2020-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

    IPC: G11C16/20 ,  G11C16/30 ,  G11C16/26

    CPC classification number: G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C2211/561

    Abstract: Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.

    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE
    79.
    发明公开
    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230145358A1

    公开(公告)日：2023-05-11

    申请号：US17978890

    申请日：2022-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/064

    Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

    STORING HIGHLY READ DATA AT LOW IMPACT READ DISTURB PAGES OF A MEMORY DEVICE
    80.
    发明申请
    STORING HIGHLY READ DATA AT LOW IMPACT READ DISTURB PAGES OF A MEMORY DEVICE 有权

    公开(公告)号：US20220342813A1

    公开(公告)日：2022-10-27

    申请号：US17302064

    申请日：2021-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Giuseppina Puzzilli ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  James Fitzpatrick ,  Shyam Sunder Raghunathan ,  Violante Moschiano ,  Tecla Ghilardi

    IPC: G06F12/02 ,  G11C29/52 ,  G11C16/34

    Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

Patent Agency Ranking