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公开(公告)号：JPS6465473A
公开(公告)日：1989-03-10
申请号：JP22158787
申请日：1987-09-04
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To utilize a valuable frequency resource by using both an FDM (frequency- division multiplex) communication system and a CDM (code-division multiplex) communication system together. CONSTITUTION:Small-sized earth stations 20-1-20-K and 40-2-40-K perform transmission to and reception from a base station 30 with assigned frequency slots by using a FDM signal. The base station 30, on the other hand, sends out a time reference at a constant period with a CMD signal. A moving body, on the other hand, has a comb-shaped filter bank which has a 1st channel as a stopping area and a 2nd channel as a passing area, so its filtering characteristics generate the CDM signal covering band width separately from the FDM signal, so that the CDM signal of narrow width of one frequency slot is outputted to a matching filter with every other frequency slot. Further, a spread spectrum modulator 11 processes the output of a data modulator 10 with a PN code synchronized with a regenerated PN clock. Further, the outputs of comb-shaped filter banks 30-1 and 30-2 are diffused reversely by matching filters 7-1 and 7-2, inputted to CDM demodulators 31-1-31-2, and inputted to a position measurement calculation part 8, so that the position measurement data are sent to the moving body.
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公开(公告)号：JPS63200636A
公开(公告)日：1988-08-18
申请号：JP3255887
申请日：1987-02-17
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04J1/05
Abstract: PURPOSE:To process a signal having a band width wider than the channel frequency interval by providing a signal interpolation circuit, a frequency shift circuit and a post-stage filter. CONSTITUTION:The output of a multiple sampling type transmultiplexer (MS- TMUX) 21 is supplied to a switch matrix 22, a signal having a wider band width than the channel frequency interval (DELTAf) is fed to interpolation circuits 23-1-23-5 and other channels are connected to interpolation circuits 23-6-23-K. For example, in reproducing a signal having a band width being twice the frequency interval DELTAf, only the (k+1)-th channel is frequency-shifted by +DELTAomega/2 and the k-th channel is frequency-shifted by -DELTAomega/2 by using the number of shifts of frequency circuits 24-1, 24-2 and the spectrums are added. The output spectrum of the adder 25-1 is outputted as it is in case of solid lines in figure and since the frequency characteristic in the vicinity of OHz is lifted in case of broken lines, then the output is supplied to a post-stage filter 26-1. Thus, the circuit having a completely flat frequency characteristic is realized for 2DELTAf.
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公开(公告)号：JPS63161714A
公开(公告)日：1988-07-05
申请号：JP30971586
申请日：1986-12-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To contrive the increase of processing speed and the number of tap by operating each circuit interposed between a serial/parallel conversion circuit and a parallel/serial conversion circuit according to 1/N clock with N frequency division of the input clock. CONSTITUTION:The titled filter is constituted of a serial/parallel conversion circuit 1 applying the input sampling string of the parallel processing and outputting a parallel output according to the input clock, an N point inverse high speed Fourier transform circuit 3, N set of sub-filters 40-4N-1 comprising a definite impulse response filters and applying filtering, an N point high speed Fourier transformation circuit 5, and a parallel/serial conversion circuit 6 outputting serially it into the input clock. Thus, a frequency divider circuit 2 sends a I/N clock being 1/N frequency division to the input clock to each circuit ands each circuit is operated according to the I/N clock being the 1/N frequency division of input clock. Thus, even if the speed of the input sampling string is large, the circuit copes easily with it.
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公开(公告)号：JPS62169555A
公开(公告)日：1987-07-25
申请号：JP1143486
申请日：1986-01-22
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H04L27/22
Abstract: PURPOSE:To attain the complete pull-in even in a narrow band PLL by adding together the outputs of both 1st and 2nd phase comparators and smoothing these added outputs to send them to a voltage control oscillator in the form of the frequency control voltage. CONSTITUTION:The frequency error discriminating output is obtained at the output of the 2nd phase comparator 15 and the detecting signal of the phase error (double) is obtained at the output of the 1st phase comparator 16 respectively. In an asynchonizing mode, the frequency error discriminating signal passes through an LPF 19, an adder 17 and an LPF 18 to control the frequency and controls the frequency error within the synchronizing range of a PLL. While the phase synchronizing operation is carried out through the PLL consisting of the comparator 16, the adder 17, the LPF 18 and a VCO 1 in a synchronizing mode. That is, the frequency error is compressed by an automatic frequency control action carried out based on the frequency discriminating action in an asynchronizing mode. Thus the complete PLL pull-in is attained.
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公开(公告)号：JPS61195016A
公开(公告)日：1986-08-29
申请号：JP3617285
申请日：1985-02-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H03H17/06
Abstract: PURPOSE:To simplify the constitution of hardware when the value of selecting property is high and to attain properly a desired characteristic in a wide frequency range by constituting a means generating a tap counting value of a read-only memory. CONSTITUTION:Digital and clock signals quantized by bits Q are inputted to the input terminal 5 of a digital filter, and the digital signal is provisionally stored by L-number of said signals connecting to a shift register 21. Its parallel output is applied to any one of L-number of multipliers 22-1-22-L, while to any one of remainders the tap counting value from the read-only memories 24-1-24-L is inputted, and the outputs of the multipliers 22-1-22-L is added by an adder 23. The clock signal is synchronized with a sampling speed, processed by an N-multiplier circuit 12 and an address counter 13, and applied to the memories 24-1-24-L as an address signal. Then the circuit constitution is simplified, and the desired characteristic can be properly attained in the side frequency range.
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Patent Agency Ranking
公开(公告)号：JPS58186247A
公开(公告)日：1983-10-31
申请号：JP6874882
申请日：1982-04-26
Applicant: Nec Corp
Inventor： ICHIYOSHI OSAMU
CPC classification number: H04J3/0605
Abstract: PURPOSE:To obtain a frame synchronizing circuit fast in pull-in operation by processing the predetermined frame statistically. CONSTITUTION:A CPU/memory circuit 14 stores the content of the 1st parallel signal PPS when a detection pulse DP generated from a synchronizing pattern detector 1 is incoming, increases the content of the corresponding memory by 1 when the content is ''1'' and decreases it by 1 when ''0'', and stores the result in the corresponding memory again to each l-bit of the said signal, allowing to integrate the content of the 1st parallel signal PPS of the l-stage shift register 13 when the pulse DP of the detector 1 is incoming. This integration is done for N frames with the count of a frame pulse FP to determine the timing of appearance of the true detection pulse generated from the detector 1 through the statistical discrimination at each N-frame. Thus, the initial frame synchronization is established at the first N-frame.
Abstract translation: 目的：通过统计处理预定帧来获得拉入操作快速的帧同步电路。 构成：当从同步模式检测器1产生的检测脉冲DP进入时，CPU /存储器电路14存储第一并行信号PPS的内容，当内容为“1”时，将相应存储器的内容增加1 并在“0”时将其减1，并将结果再次存储在相应的存储器中，使其能够整合到所述信号的每个1比特，从而将1级移位寄存器13的第1并行信号PPS的内容 当检测器1的脉冲DP进入时。 对于具有帧脉冲FP的计数的N帧进行该积分，以通过每个N帧的统计鉴别确定从检测器1产生的真实检测脉冲的出现定时。 因此，在第一N帧建立初始帧同步。
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公开(公告)号：JP2001320342A
公开(公告)日：2001-11-16
申请号：JP2000138181
申请日：2000-05-11
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PROBLEM TO BE SOLVED: To integrate broadcasting of an FDM method and the communication of a CDMA method. SOLUTION: A diffusion code setting circuit 3 generates N pieces of vectors, whose polarities are each +1 or -1 which are specific to a communication user. A multiplier 4-n multiplies the N-th data by the N-th diffusion code corresponding to the data to perform diffusion modulation. An FDM synthesis circuit 5 modulates N pieces of data in the FDM method. An FDM separation circuit 8 demodulates a received signal in the FDM method. An inverse diffusion code setting circuit 9 generates N pieces of vectors, whose polarities are each +1 or -1 and which are proper to the user of a transmitting side. A multiplier 10-N multiplies the n-th data by the N-th inverse diffusion code corresponding to the data to perform inverse diffusion modulation.
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公开(公告)号：JPH0879167A
公开(公告)日：1996-03-22
申请号：JP20570794
申请日：1994-08-30
Applicant: NEC CORP
Inventor： NISHIYAMA TAKEHIRO , ICHIYOSHI OSAMU
Abstract: PURPOSE: To provide a radio communication broadcast system which includes the control and broadcast channels of time division multiplex constitution and can be immediately switched to a talking mode when a call is received from another mobile station. CONSTITUTION: A mobile station demodulates the broadcast signals by an FM demodulator 9 and broadcasts these demodulated signals through a speaker 17 and via a time expander 12, a switch 14 and a CODEC 15. When an off-hook state of a telephone set 16 is detected at either one of mobile stations, the broadcast output of the speaker 17 is discontinued and the dial information is sent to a radio base station. Then the calling and called mobile stations receive the idle channel numbers sent from the radio base station through each control slot that undergone the time division multiplexing. Thus each of both mobile stations performs the talking through a communication channel after the switching of the transmission/reception frequency. When the talking is over and the on-hook signal of the telephone set 16 is detected, the control and broadcast channels are reset. Then the end of the talking is notified to a channel control processor of the radio base station.
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公开(公告)号：JPH07154354A
公开(公告)日：1995-06-16
申请号：JP29584193
申请日：1993-11-26
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To simplify the synchronizing means of TDM multiplex data concerning the FDM/TDM conversion reproducing repeating method for mutually performing communication while using plural miniaturized stations and a reproducing repeater station. CONSTITUTION:An FDM/TDM conversion reproducing device 83 is used for the reproducing repeater station, and an FDM signal inputted from a receiver 3 is inputted to a transmultiplexer type branching filter circuit 4 and separated for each channel. Each separated signal recognizes a demodulating operation, TDM frame signal and time difference information (Te) of a TMUX output timing signal at individually provided demodulation circuits 81 of 1-N and after the synchronizing operation is performed to a TDM frame signal, a TDM signal is provided.
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公开(公告)号：JPH0646094A
公开(公告)日：1994-02-18
申请号：JP19573592
申请日：1992-07-23
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: PURPOSE:To realize a unique word detection circuit which is stably operated even when a frequency of a receiver has an error against to a frequency of a reception signal. CONSTITUTION:A local oscillator 1 almost tuned to a reception signal implements quasi-synchronization detection to convert the signal into a complex specified band signal, and A/D converters 6,7 sample and implement A/D conversion to the signal. The sampled value is inputted to shift registers 8,9 for N- sample length. On the other hand, a unique word pattern generator 11 generates a known unique word pattern in a complex number form and the pattern is subject to complex multiplication with each tap signal from the shift registers at complex multipliers 101-10n. A filter group 12 receiving N sets of parallel outputs from the complex multipliers implements the FFT arithmetic operation then the absolute values of the N-sets of the outputs subject to FFT arithmetic operation are compared and it is discriminated that the unique work is in existence in the presence of an output of the absolute value larger than a mean value by a specified threshold value and a frequency error of the reception signal is simultaneously detected from its output terminal in this unique word detection circuit.
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