公开(公告)号：JPH01302749A

公开(公告)日：1989-12-06

申请号：JP13236188

申请日：1988-05-30

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L23/52 ,  H01L21/3205

Abstract: PURPOSE:To form a super-high integrated circuit of excellent reliability having no after-corrosion by a method wherein, after a barrier metal has been formed, a prescribed pattern is formed, and a metal wiring is formed on a barrier metal pattern. CONSTITUTION:A barrier metal layer 2 is formed directly on an SiO2 substrate 1. A prescribed resist pattern 4, corresponding to a barrier metal pattern, is formed on the Ti/TiN barrier metal layer 2 using a photo-lithographic technique. The barrier metal layer 2 is etched using the pattern 4 as a mask. The pattern 4 is exfoliated. As a result, the structure wherein a prescribed barrier pattern 21 is formed on the substrate 1 can be obtained. A wiring layer 3 is formed on the pattern 21. Consequently, a laminated structure, which is called a barrier metal/metal wiring, is not exposed to the side wall. Accordingly, an after- corrosion is removed, and the wiring layer 3 of super-high integrated circuit can be formed in a highly reliable manner.

公开(公告)号：JPS6455257A

公开(公告)日：1989-03-02

申请号：JP21335087

申请日：1987-08-27

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: B41J2/335 ,  B41J2/345

Abstract: PURPOSE:To enable a resistant value to be controlled without alteration of generating conditions of a resistor layer by a method wherein the thermal resistor layer becoming a printing part has a groove part as a resistance regulation area. CONSTITUTION:Groove parts 5 are formed on both sides (or on one side) between a thermal resistor layer 3a becoming a printing part 2 and an electrode 4 in a heat accumulating layer (a glaze layer) 1 formed on a substrate, and a resistor layer 3 in the groove part 5 is taken as a resistance area. Although an area of the thermal resistor layer 3a is not varied by preliminarily varying the depth (d) of the groove part 5, a resistance value can be controlled by varying relatively an area of the resistance layer 3 in the groove part 5. Further, by varying the number of the groove parts 6 in the thermal resistor layer 3a, that is, an areal ratio of an upper surface becoming the actual thermal resistor layer 3a and a bottom surface of the groove part 6, the resistance value can be controlled. Further, by trimming a portion of the resistor layer 3 at the bottom part by using a mask without varying the depth of the groove part 5, the resistance value can be controlled.

公开(公告)号：JPS6436023A

公开(公告)日：1989-02-07

申请号：JP19163687

申请日：1987-07-31

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: C23F4/00 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To execute an etching operation without leaving a remaining substance and under a condition of a high selection ratio with reference to a substratum layer by a method wherein the etching operation by using a chlorine gas and the etching operation by using a fluorine gas are combined. CONSTITUTION:When a dry etching operation is executed to a laminated conductive film 5 composed of a refractory metal silicon compound layer 3 formed on a substrate 1 and an aluminum layer 4 formed on this refractory metal silicon compound layer 3, a whole part of the aluminum layer 4 and one part of the refractory metal silicon compound layer 3 are etched selectively by using a chlorine (Cl) gas; a remaining part of the refractory metal silicon compound layer 3 is etched by using a fluorine (F) gas. A refractory metal silicon compound refers to, e.g., MoSi2, WSi12, TaSi2 or the like. As the chlorine gas, e,g., a gas mainly composed of BCl3 is used; as the fluorine-based gas, e.g., a gas composed of SF6 is used.

公开(公告)号：JPS6310522A

公开(公告)日：1988-01-18

申请号：JP15416786

申请日：1986-07-02

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  HOZUMI HIROKI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To enable a smooth etched surface having no residue to be formed, by cooling a lower electrode on which a wafer is mounted and then making an upper electrode facing the lower electrode be etched in a state where the temperature of the upper electrode is higher than that of the lower electrode. CONSTITUTION:In a dry etching method in which fluorine-group gases and oxygenous gases are used as etching gases and a parallel-flat plate device is used, a lower electrode on which a wafer is mounted is cooled and then an upper electrode facing the lower electrode is etched in a state where the temperature of the upper electrode is higher than that of the lower electrode. For example, a plasma nitride (P-SiN) film 2 is piled on an Al wiring 1, and a resist 3 is then piled thereon for a flattening process. Successively, when a sample (c) is put and etched in a conventional RIE device, the lower electrode (on the cathode side) on which the wafer is mounted is cooled as it is by using tap water, and the water flowing on the upper electrode (on the anode side) is made to pass through a heat exchanger so as to be heated at 50 deg.C. Hence, a very smooth etched surface having no residue can be formed.

公开(公告)号：JPS62232925A

公开(公告)日：1987-10-13

申请号：JP7691586

申请日：1986-04-03

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To etch Si controllably, by using a mixed gas, in which a fluoride gas and a hydrocarbon gas are mixed and chlorine is not contained, as a gas for etching Si so that a trench is prevented from being excessively shaved on its lower part. CONSTITUTION:A gas for etching Si is formed of a mixing gas, in which a fluoride gas and a hydro carbon gas are mixed and chlorine is not contained. NF3, SF6, or the like are used for said fluoride gas. CH3F, CH2F2, CHF3, C2H2, C2H4, or the like, which does not contain Cl in their constituents, are used for said hydro carbon gas. Then, carbon is piled on the sidewall of the trench 3 etched, and the carbon as a protective material prevents a fluorine radical F* from being side-attacked. Hence, the trench 3 can be prevented from being excessively shaved on its lower part, capable of etching the Si controllably.

公开(公告)号：JPS6240729A

公开(公告)日：1987-02-21

申请号：JP17861685

申请日：1985-08-15

Applicant: SONY CORP

Inventor： SATO JUNICHI ,  SHINOHARA KEIJI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To obtain an etching device capable of preserving an anisotropy while using O2 plasma by disposing a material which contains an element for collecting an oxygen radical in reaction with the radical near an electrode material. CONSTITUTION:A cathode material 2 is formed of a hydrocarbon resin to form an etching table, and a wafer 3 is placed on a cathode 1. An etching gas for forming atmosphere gas 5 at etching time can use, for example, a mixture of CF4, O2 and, as required inert gas such as CO2, N, Ar. Thus, a problem of causing an undercut is solved to attain an accurate and ultrafine working.

公开(公告)号：JPS6224627A

公开(公告)日：1987-02-02

申请号：JP16296085

申请日：1985-07-25

Applicant: SONY CORP

Inventor： SATO JUNICHI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To reduce undercut with a simplified method by providing a material part which controls amount of fluorine radical within the etching reaction chamber. CONSTITUTION:A cathode material 2 which forms a cathode 1 is formed by a hydrogen carbide system resin and a base material Si wafer which forms a material 3 to be etched is coated with a resist. For example, an etching stop layer 32 is formed of SiO2 and SiN layer on a base material Si 31, the resist is patterned on the etching stop layer 32 and a sample to be etched is formed by eliminating the etching stop layer 32 by etching with the resist used as the mask. When this material 3 to be etched is etched by REI using the F base gas, an extra F radical may be seized by the cathode material 2 and resist material 33. Thereby over etching can be prevented and etching with high controllability for shape can be realized. Accordingly, the shape of etching of material to be etched can be controlled with a simplified means and generation of undercut may also be controlled.

公开(公告)号：JPS61230324A

公开(公告)日：1986-10-14

申请号：JP7183685

申请日：1985-04-04

Applicant: SONY CORP

Inventor： HAYASHI HISAO ,  WATANABE KATSURA ,  NAKAJIMA TAKESHI ,  SATO JUNICHI

IPC: H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To form openings in an object to be etched which are narrower by the width of the layers of a predetermined substance by forming a layer of a predetermined substance on the inner wall of the openings of a film which has openings on an object to be etched, and with the layers of a predetermined substance as a mask, anisotropically etching the object to be etched. CONSTITUTION:Resist 8 having openings 8a, 8b is formed on, e.g., an SiO2 film 7, and SiO2 films 9a, 9b are formed on the inner wall of the openings 8a, 8b. Then,with the SiO2 films 9a, 9b as a mask the SiO2 film 7 is anisotropically etched, thereby forming openings 7a, 7b. With this, the openings 7a, 7b can be formed which are narrower in width than the width of the openings 8a, 8b of the photo resist 8 by a length corresponding to two times of the width of the SiO2 films 9a, 9b formed on the inner walls of the openings 8a, 8b of the resist 8, and fine processing is thus possible.

公开(公告)号：JPS6174341A

公开(公告)日：1986-04-16

申请号：JP19731584

申请日：1984-09-20

Applicant: Sony Corp

Inventor： SHINOHARA KEIJI ,  SATO JUNICHI

IPC: H01L21/302 ,  H01L21/3065

CPC classification number: H01L21/302

Abstract: PURPOSE:To make it feasible to detect the etching terminal of semiconductor substrate accurately by a method wherein a substrate for measurement wherein a material layer to be etched during the same time as that of another substrate to be etched is provided on a reaction layer is etched simultaneously in the same reaction chamber. CONSTITUTION:When a single crystal Si substrate 1 is etched down to the depth d1, the etching time is equivalent to the etching time required for etching the substrate 1 down to the depth d1. A polycrystalline Si layer 3 of thickness d1 is formed on an SiO2 layer 2 making reaction at interface and then another surface 4 for measurement is provided. Then the substrates 1 and 4 arranged in the same reaction chamber 5 are simultaneously etched while irradiating the substrate 4 with laser beams 7. Finally interference light 8 emitted by reaction on the surface and interface of layer 3 of substrate 4 may be detected to perform etching process until interference wave forms are eliminated.

Abstract translation: 目的：为了能够通过以下方法精确地检测半导体衬底的蚀刻端子是可行的：其中在反应层上设置用于测量其中待蚀刻的材料层与待蚀刻的另一衬底相同时间的材料层的方法， 同时在同一个反应室。 构成：当将单晶Si衬底1蚀刻到深度d1时，蚀刻时间等于蚀刻衬底1直至深度d1所需的蚀刻时间。 在SiO 2层2上形成厚度为d1的多晶硅层3，在界面处进行反应，然后提供另一个用于测量的表面4。 然后，在激光束7照射基板4的同时，同时蚀刻配置在同一反应室5中的基板1和4.最后，可以检测通过反应在基板4的表面和界面上发生的干涉光8进行蚀刻 过程直到干扰波形被消除。

公开(公告)号：JPS6126239A

公开(公告)日：1986-02-05

申请号：JP14618384

申请日：1984-07-14

Applicant: Sony Corp

Inventor： SATO JUNICHI ,  SHINOHARA KEIJI

IPC: H01L27/08 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/76

Abstract: PURPOSE:To enhance the effect of isolation without increasing the depth, by a method wherein an interelement isolation layer is formed by inclination from the direction vertical to a substrate. CONSTITUTION:A vertical stepwise difference 16a is prepared by reactive ion etching on an SiO2 16 on the Si substrate 1 and then covered with a CVD SiO2 17, thus forming a crack 17a. On the RIE, window 18 is opened 18 obliquely in the direction of elongation of the crack 17a. At this time, if the leftmost end (a) of the film 17 projects to the left from the rightmost end (b) of the substrate 1, an oblique groove can be smoothly formed. Next, a groove 14 of desired depth is formed by reactive ion etching of the Si substrate 1, using the film 17 as a mask, and is then filled with CVD SiO2 15. The N type Si substrate 1 is provided with a P-well 5 and an oblique insulation isolation layer 15 of this construction, thus providing an NchMOSFET3 and a PchMOSFET4 to form a CMOSIC, when the path of a parasitic SCR is by-passed long and comes difficult to latch up.

Abstract translation: 目的：为了增加隔离效果而不增加深度，通过一种方法，其中通过垂直于衬底的方向倾斜地形成非线性隔离层。 构成：通过在Si衬底1上的SiO 2 16上的反应离子蚀刻制备垂直的阶梯差16a，然后用CVD SiO 2 17覆盖，从而形成裂纹17a。 在RIE上，窗口18沿着裂纹17a的伸长方向倾斜地开口18。 此时，如果薄膜17的最左端（a）从基板1的最右端（b）向左侧突出，则能够平滑地形成斜槽。 接下来，使用膜17作为掩模，通过Si衬底1的反应离子蚀刻形成所需深度的凹槽14，然后用CVD SiO 2 15填充.N型Si衬底1设置有P阱 5和这种结构的倾斜绝缘隔离层15，因此当寄生SCR的路径被绕过很长并且难以闭锁时，提供NchMOSFET3和PchMOSFET4以形成CMOSIC。