公开(公告)号：JP2015050305A

公开(公告)日：2015-03-16

申请号：JP2013180722

申请日：2013-08-30

Applicant: 株式会社東芝 ,  Toshiba Corp

Inventor： ISOBAYASHI ATSUNOBU ,  KAJITA AKIHIRO ,  SAKAI TADASHI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/49877 ,  H01L21/00 ,  H01L21/76885 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 【課題】半導体装置に用いるグラフェン配線の低抵抗化をはかる。【解決手段】コンタクトビア13を有する半導体基板10上に、コンタクトビア13に接続されるように形成され、一つの側壁面を除く部分が絶縁膜16,21で覆われた触媒金属層15と、触媒金属層15の絶縁膜16,21で覆われていない側壁面からの成長により基板表面と平行方向に形成された多層グラフェン層20と、を具備した。【選択図】図1

Abstract translation: 要解决的问题：为了实现用于半导体器件的石墨烯布线的低电阻。解决方案：半导体器件包括：催化剂金属层15，其形成在具有接触通孔13的半导体衬底10上，以连接到触点 并且除了一个侧壁表面以外的部分覆盖有绝缘膜16,21; 以及多层石墨烯层20，其通过从未被绝缘膜16,21覆盖的催化剂金属层15的侧壁表面生长而与基板表面平行地形成。

公开(公告)号：JP2014157923A

公开(公告)日：2014-08-28

申请号：JP2013027925

申请日：2013-02-15

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： WADA MAKOTO ,  MIYAZAKI HISAO ,  KAJITA AKIHIRO ,  ISOBAYASHI ATSUNOBU ,  SAITO TATSURO ,  SAKAI TADASHI

IPC: H01L27/10 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/532 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/1606 ,  H01L21/3215 ,  H01L21/76805 ,  H01L21/76876 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/53276 ,  H01L27/1052 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To achieve low resistance of graphene wiring without causing etching or corrosion of a metallic material thereby to contribute to improvement in device characteristics.SOLUTION: A semiconductor device using graphene wiring comprises: a substrate 10 on which a semiconductor element is formed; first multilayer graphene wiring 20a which is formed above the substrate 10 and includes impurity-doped multilayer graphene layers 23a; second multilayer graphene wiring 20b which includes non-doped multilayer graphene layers 23b which are formed above the substrate 10 and in the same layer with the first multilayer graphene wiring 20a; a lower layer contact 15 connected to an undersurface of each of the first multilayer graphene wiring 20a; and an upper layer contact 33 connected to a top face of the second multilayer graphene wiring 20b.

Abstract translation: 要解决的问题：为了实现石墨烯布线的低电阻而不引起金属材料的蚀刻或腐蚀，从而有助于改善器件特性。解决方案：使用石墨烯布线的半导体器件包括：形成有半导体元件的基板10 ; 第一多层石墨烯布线20a，其形成在基板10上方，并且包括杂质掺杂多层石墨烯层23a; 第二多层石墨烯布线20b，其包括形成在基板10上方并且与第一多层石墨烯布线20a在同一层中的非掺杂多层石墨烯层23b; 连接到每个第一多层石墨烯布线20a的下表面的下层接触件15; 以及连接到第二多层石墨烯布线20b的顶面的上层接触33。

公开(公告)号：JP2014107454A

公开(公告)日：2014-06-09

申请号：JP2012260233

申请日：2012-11-28

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SUZUKI MARIKO ,  SAKAI TADASHI ,  SAKUMA HISASHI ,  KATAGIRI MASAYUKI ,  YAMAZAKI YUICHI

IPC: H01L29/868 ,  H01L21/329 ,  H01L21/336 ,  H01L21/338 ,  H01L29/47 ,  H01L29/78 ,  H01L29/812 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L29/1602 ,  H01L21/02376 ,  H01L21/02433 ,  H01L21/02444 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02527 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/041 ,  H01L21/042 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/6603 ,  H01L29/66045 ,  H01L29/78 ,  H01L29/8128 ,  H01L29/868 ,  H01L29/872

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that includes diamond semiconductor layers with controlled impurity concentration, and has low on-resistance and high withstand voltage.SOLUTION: A semiconductor device includes: a first diamond semiconductor layer of a first conductivity type having a primary surface with a first surface orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower impurity concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher impurity concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

Abstract translation: 要解决的问题：提供一种半导体器件，其包括具有可控杂质浓度的金刚石半导体层，并且具有低导通电阻和高耐压。解决方案：半导体器件包括：第一导电类型的第一金刚石半导体层，其具有 主表面具有第一表面取向; 形成在所述第一金刚石半导体层中的沟槽结构; 形成在所述沟槽结构中的所述第一金刚石半导体层上并且具有比所述第一金刚石半导体层更低的杂质浓度的第二金刚石半导体层; 第二导电类型的第三金刚石半导体层形成在第二金刚石半导体层上并且具有比第二金刚石半导体层更高的杂质浓度; 电连接到第一金刚石半导体层的第一电极; 以及与第三金刚石半导体层电连接的第二电极。

公开(公告)号：JP2013058669A

公开(公告)日：2013-03-28

申请号：JP2011196955

申请日：2011-09-09

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KATAGIRI MASAYUKI ,  YAMAZAKI YUICHI ,  WADA MAKOTO ,  SAKAI TADASHI ,  SAKUMA HISASHI ,  SUZUKI MARIKO

IPC: H01L21/3205 ,  C01B31/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufactured by a method of a simple manufacturing process.SOLUTION: A semiconductor device according to an embodiment comprises: a substrate; a catalyst metal film on the substrate; a graphene on the catalyst metal film; an interlayer insulation film on the graphene; a contact hole penetrating the interlayer insulation film; and carbon nanotubes provided in the contact hole on the catalyst metal film processed by plasma of one and more gases selected from hydrogen, nitrogen, ammonia, and an inert gas, or carbon nanotubes penetrating the interlayer insulation film on the catalyst metal film processed by plasma of one and more gases selected from hydrogen, nitrogen, ammonia, and an inert gas.

Abstract translation: 要解决的问题：提供通过简单制造方法制造的半导体器件。 解决方案：根据实施例的半导体器件包括：衬底; 基板上的催化剂金属膜; 催化剂金属膜上的石墨烯; 石墨烯上的层间绝缘膜; 穿透层间绝缘膜的接触孔; 以及设置在催化剂金属膜上的接触孔中的碳纳米管，其通过从氢，氮，氨和惰性气体中选择的一种或多种气体的等离子体处理，或者穿过在等离子体处理的催化剂金属膜上的层间绝缘膜的碳纳米管 的一种或多种选自氢，氮，氨和惰性气体的气体。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012199520A

公开(公告)日：2012-10-18

申请号：JP2012036376

申请日：2012-02-22

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： KITAMURA MASAYUKI ,  SAKATA ATSUKO ,  WADA MAKOTO ,  YAMAZAKI YUICHI ,  KATAGIRI MASAYUKI ,  KAJITA AKIHIRO ,  SAKAI TADASHI ,  SAKUMA HISASHI ,  MIZUSHIMA ICHIRO

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/02639 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/02645 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53276 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device including a high quality graphene having crystal defect as less as possible and resistance lower than the related art.SOLUTION: A semiconductor device comprises: a semiconductor substrate; and wiring provided above the semiconductor substrate. A portion of a promoter layer, which contacts a catalyst layer has a face-centered cubic structure or a hexagonal close-packed structure, and (111) face of the face-centered cubic structure or (002) face of the hexagonal close-packed structure is directed parallel to a surface of the semiconductor substrate. Alternatively, the portion of the promoter layer, which contacts the catalyst layer has an amorphous structure or a microcrystalline structure. The catalyst layer has a face-centered cubic structure or a hexagonal close-packed structure, and (111) face of the face-centered cubic structure or (002) face of the hexagonal close-packed structure is directed parallel to the surface of the semiconductor substrate.

Abstract translation: 要解决的问题：提供一种半导体器件，其包括具有尽可能低的晶体缺陷的高品质石墨烯和比现有技术更低的电阻。 解决方案：半导体器件包括：半导体衬底; 以及设置在半导体基板上方的布线。 与催化剂层接触的助催化剂层的一部分具有面心立方结构或六方密堆积结构，并且六面体密堆积的（111）面的面心立方结构或（002）面 结构指向与半导体衬底的表面平行。 或者，与催化剂层接触的促进剂层的部分具有非晶结构或微晶结构。 催化剂层具有面心立方结构或六方密堆积结构，并且六边形密堆积结构的面心立方结构的（111）面或（002）面的平行于 半导体衬底。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012109632A

公开(公告)日：2012-06-07

申请号：JP2012055116

申请日：2012-03-12

Applicant: TOSHIBA CORP

Inventor： MATSUNAGA NORIAKI ,  WADA MAKOTO ,  AKIMOTO YOSUKE ,  SAKAI TADASHI ,  SAKUMA HISASHI ,  KATAGIRI MASAYUKI ,  YAMAZAKI YUICHI

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a carbon nanotube wiring capable of acquiring an excellent electric connection in a plug wiring having a carbon nanotube.SOLUTION: A manufacturing method of a carbon nanotube wiring comprises: a step of forming an interlayer insulating film 13 on a first wiring layer 12; a step of forming a contact hole 15 in the interlayer insulating film on the first wiring layer; a step of growing a carbon nanotube 16 on the first wiring layer in the contact hole and forming a plurality of carbon nanotubes protruding from a tip of the contact hole; a step of forming a stopper film 17 on the interlayer insulating film and between the plurality of the carbon nanotubes; a step of forming an insulating film on the stopper film and the plurality of the carbon nanotubes; a step of removing the plurality of the carbon nanotubes on the contact hole together with the insulating film on the stopper film using the stopper films as stoppers; and a step of forming a second wiring layer 14 on the plurality of the carbon nanotubes.

公开(公告)号：JP2012049268A

公开(公告)日：2012-03-08

申请号：JP2010188836

申请日：2010-08-25

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAKUMA HISASHI ,  SAKAI TADASHI ,  YAMAZAKI YUICHI ,  KATAGIRI MASAYUKI ,  SUZUKI MARIKO ,  WADA MAKOTO

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor substrate solving the problem in which an embedded film formed in a via-hole, for embedding a carbon nanotube, is not uniformly formed in the substrate, thereby causing an interlayer insulating film to be ununiformly polished at a planarization treatment step to produce a short-circuit between an underlying interconnection and an upper electrode at a position other than via wiring.SOLUTION: A method for manufacturing a semiconductor substrate comprises: forming a carbon nanotube in a via-hole formed in an interlayer insulating film in a semiconductor substrate; thereafter, subjecting the entire substrate to fluorination treatment; then forming an embedded film only in the via-hole having the carbon nanotube therein; and thereafter, polishing the substrate for planarization treatment of the entire substrate. Accordingly, the interlayer insulating film is prevented from being locally polished.

Abstract translation: 解决问题的方案：为了提供一种解决在基板中不均匀地形成用于嵌入碳纳米管的通孔中形成的嵌入膜的半导体基板的制造方法，由此形成中间层 绝缘膜在平坦化处理步骤中被不均匀地抛光，以在除了通孔布线之外的位置处产生下面的互连和上电极之间的短路。 解决方案：一种用于制造半导体衬底的方法包括：在形成在半导体衬底中的层间绝缘膜中的通孔中形成碳纳米管; 然后对整个基板进行氟化处理; 然后仅在其中具有碳纳米管的通孔中形成嵌入膜; 然后对整个基板进行平面化处理用基板的研磨。 因此，防止了层间绝缘膜的局部抛光。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2010212619A

公开(公告)日：2010-09-24

申请号：JP2009059869

申请日：2009-03-12

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： YAMAZAKI YUICHI ,  WADA MAKOTO ,  SAKAI TADASHI ,  MATSUNAGA NORIAKI ,  SAKUMA HISASHI ,  KATAGIRI MASAYUKI ,  SUZUKI MARIKO

IPC: H01L21/205

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for manufacturing a graphene structure suited for a semiconductor manufacturing process.
SOLUTION: The method includes: a first step of supplying a first plasma generated from a first gas containing at least hydrogen or one of rare gas to a thin film containing at least one of Co, Ni, Fe carried by a substrate 30; a second step of generating a second plasma containing radical from a second gas containing a hydrocarbon-based gas, and supplying the radical of the second plasma to the thin film through a plane electrode 4 which intercepts penetration of the second plasma other than the radical; and a third step of supplying a third plasma generated from a third gas containing a rare gas to the thin film.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于制造适于半导体制造工艺的石墨烯结构的方法和装置。 解决方案：该方法包括：第一步骤，将由至少含有氢或一种稀有气体的第一气体产生的第一等离子体供给到由衬底30承载的至少一种Co，Ni，Fe的薄膜 ; 从含有烃基气体的第二气体产生含有自由基的第二等离子体的第二步骤，并且通过拦截第二等离子体而不是自由基的平面电极4将第二等离子体的基团供给薄膜; 以及第三步骤，将从含有稀有气体的第三气体产生的第三等离子体提供给薄膜。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009033021A

公开(公告)日：2009-02-12

申请号：JP2007197353

申请日：2007-07-30

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAKAI TADASHI ,  SAKUMA HISASHI ,  KATAGIRI MASAYUKI ,  SUZUKI MARIKO

IPC: H01L21/60 ,  C01B31/02 ,  H01H59/00 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/06

CPC classification number: H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To provide a structure for preventing a carbon nanotube bundle from spreading. SOLUTION: The structure includes a conductive film 12 formed in a base layer 10 and a plurality of carbon nanotube CNT bundles 20 an end of which is connected to the conductive film 12. At least the carbon nanotube at an external side portion of the CNT bundle 20 out of a plurality of carbon nanotubes is extended to the exterior of the CNT bundle having a convex curvature at an other end of the CNT bundle 20. The curvature becomes larger in a direction of the perimeter of the CNT bundle, the bundle diameter being smaller in a direction of the other end thereof. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种防止碳纳米管束扩散的结构。 解决方案：该结构包括形成在基底层10中的导电膜12和多个碳纳米管CNT束20，其端部连接到导电膜12上。至少在碳纳米管的外侧部分 多个碳纳米管中的CNT束20在CNT束20的另一端延伸到具有凸曲率的CNT束的外部。曲率在CNT束的周边方向上变大， 束直径在其另一端的方向上较小。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009026594A

公开(公告)日：2009-02-05

申请号：JP2007188333

申请日：2007-07-19

Applicant: Toshiba Corp ,  株式会社東芝

Inventor： SAKAI TADASHI ,  NAKANO YOSHIHIKO ,  TAMURA ATSUSHI ,  SAKUMA HISASHI ,  ONO TOMIO

IPC: H01J1/304 ,  H01J9/02 ,  H01J29/04 ,  H01J63/08

Abstract: PROBLEM TO BE SOLVED: To provide: an electron source that achieves electron emission at low voltage, stable operation and high reliability; a method for manufacturing the electron source; and a discharge device such as a cold cathode discharge lamp using the electron source. SOLUTION: An electron source 1 has a substrate 2, an aggregate of diamond crystal particles 3 that is formed on the substrate 2, and platinum particles 4 formed on the top surface of the diamond crystal particles 3. The electron source 1 is used for a discharge device such as a cold cathode discharge lamp. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供：在低电压，稳定运行和高可靠性下实现电子发射的电子源; 一种制造电子源的方法; 以及使用电子源的诸如冷阴极放电灯的放电装置。 解决方案：电子源1具有基板2，形成在基板2上的金刚石晶体颗粒3的聚集体和形成在金刚石晶体颗粒3的顶表面上的铂颗粒4.电子源1是 用于诸如冷阴极放电灯的放电装置。 版权所有（C）2009，JPO＆INPIT