公开(公告)号：US20130256701A1

公开(公告)日：2013-10-03

申请号：US13905148

申请日：2013-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US10446447B2

公开(公告)日：2019-10-15

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

公开(公告)号：US20190267492A1

公开(公告)日：2019-08-29

申请号：US16413425

申请日：2019-05-15

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/45

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US10347716B2

公开(公告)日：2019-07-09

申请号：US15786611

申请日：2017-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/283

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

公开(公告)号：US10141193B2

公开(公告)日：2018-11-27

申请号：US14949896

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

公开(公告)号：US20180323302A1

公开(公告)日：2018-11-08

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

公开(公告)号：US10056490B1

公开(公告)日：2018-08-21

申请号：US15496000

申请日：2017-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which a sidewall of the fin-shaped structure comprises a curve. Specifically, the fin-shaped structure includes a top portion and a bottom portion, a shallow trench isolation (STI) around the bottom portion of the fin-shaped structure, and the curve includes a planar portion extending from the top surface of fin-shaped structure downward and a curved portion extending from the bottom surface of the fin-shaped structure upward.

公开(公告)号：US10014227B2

公开(公告)日：2018-07-03

申请号：US14825165

申请日：2015-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC: H01L27/092 ,  H01L21/84 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

公开(公告)号：US20180138263A1

公开(公告)日：2018-05-17

申请号：US15350453

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Yen-Chen Chen ,  Chin-Fu Lin ,  Chun-Yuan Wu ,  Chun-Ling Lin

IPC: H01L49/02

CPC classification number: H01L28/75

Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.

公开(公告)号：US09972644B2

公开(公告)日：2018-05-15

申请号：US14872156

申请日：2015-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/12 ,  H01L27/12 ,  H01L29/786 ,  H01L29/51 ,  H01L29/24 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L21/768

CPC classification number: H01L27/1237 ,  H01L21/02107 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.