公开(公告)号：US10062700B2

公开(公告)日：2018-08-28

申请号：US15458946

申请日：2017-03-14

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang ,  Hsien-Shih Chu

IPC: H01L27/108

CPC classification number: H01L27/1085 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10894

Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.

公开(公告)号：US10043812B1

公开(公告)日：2018-08-07

申请号：US15726369

申请日：2017-10-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/06 ,  H01L21/311

Abstract: A method of fabricating a semiconductive structure with a word line includes providing a substrate including a memory cell region and a peripheral region. A first trench and second trench are formed within the memory cell region, and a third trench is formed within the peripheral region. A width of the first trench is smaller than the second trench, and the width of the second trench is smaller than the third trench. A first silicon oxide layer fills up the first trench. A silicon nitride layer fills up the second trench and covers the third trench. A second silicon oxide layer is formed in the third trench. Part of the substrate within the memory cell region, part of the first silicon oxide layer, and part of the silicon nitride layer are removed to form a word line trench. Finally, a word line is formed in the word line trench.

公开(公告)号：US09985123B2

公开(公告)日：2018-05-29

申请号：US15602087

申请日：2017-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US09773890B2

公开(公告)日：2017-09-26

申请号：US14919716

申请日：2015-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US20170263744A1

公开(公告)日：2017-09-14

申请号：US15602087

申请日：2017-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US09711411B2

公开(公告)日：2017-07-18

申请号：US14963216

申请日：2015-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Shih-Fang Tzou ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/31116 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.

公开(公告)号：US20170200811A1

公开(公告)日：2017-07-13

申请号：US15470905

申请日：2017-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

公开(公告)号：US09698255B2

公开(公告)日：2017-07-04

申请号：US14681119

申请日：2015-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

公开(公告)号：US09640484B2

公开(公告)日：2017-05-02

申请号：US14882424

申请日：2015-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

公开(公告)号：US09548239B2

公开(公告)日：2017-01-17

申请号：US14612235

申请日：2015-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract translation: 首先在衬底上形成栅极结构，并且在栅极结构周围形成层间电介质（ILD）层，在ILD层和栅极结构上形成介电层，在介电层和ILD层中形成开口 并且在介质层和开口中形成有机电介质层（ODL）。 在去除部分ODL后，部分电介质层延伸开口，然后剩余的ODL，在开口处形成接触塞。