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公开(公告)号：US09076759B2
公开(公告)日：2015-07-07
申请号：US13737949
申请日：2013-01-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Wei Chen , Chien-Chung Huang , Kok Seen Lew
CPC classification number: H01L29/66795 , H01L21/26506 , H01L21/28518 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0847 , H01L29/401 , H01L29/41766 , H01L29/41791 , H01L29/4232 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a semiconductor substrate, a metal gate structure, at least an epitaxial layer, an interlayer dielectric, at least a contact hole, at least a metal silicide layer and a fluorine-containing layer. The semiconductor substrate has at least a gate region and at least a source/drain region adjoining the gate region. The gate structure is disposed on the semiconductor substrate within the gate region. The epitaxial layer is disposed on the semiconductor substrate within the source/drain region. The interlayer dielectric covers the semiconductor substrate, the gate structure and the epitaxial layer. The contact hole penetrates the interlayer dielectric to reach the epitaxial layer. The metal silicide layer is formed in the epitaxial layer and is located on the bottom of the contact hole. The fluorine-containing layer is disposed on or in the epitaxial layer and is around sides of the metal silicide layer.
Abstract translation: 半导体器件包括半导体衬底，金属栅极结构，至少外延层，层间电介质，至少接触孔，至少金属硅化物层和含氟层。 半导体衬底至少具有栅极区域和至少与栅极区域相邻的源极/漏极区域。 栅极结构设置在栅极区域内的半导体衬底上。 外延层设置在源极/漏极区域内的半导体衬底上。 层间电介质覆盖半导体衬底，栅极结构和外延层。 接触孔穿透层间电介质到达外延层。 金属硅化物层形成在外延层中并且位于接触孔的底部。 含氟层设置在外延层中或外延层中并且在金属硅化物层的侧面附近。
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公开(公告)号：US11251187B2
公开(公告)日：2022-02-15
申请号：US15712151
申请日：2017-09-22
Inventor： Pin-Hong Chen , Yi-Wei Chen , Tzu-Chieh Chen , Chih-Chieh Tsai , Chia-Chen Wu , Kai-Jiun Chang , Yi-An Huang , Tsun-Min Cheng
IPC: H01L27/108
Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
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公开(公告)号：US10943909B2
公开(公告)日：2021-03-09
申请号：US16001949
申请日：2018-06-07
Inventor： Yi-Wei Chen , Hsu-Yang Wang , Chun-Chieh Chiu , Shih-Fang Tzou
IPC: H01L27/108 , H01L21/76 , H01L21/768
Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
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公开(公告)号：US10811272B2
公开(公告)日：2020-10-20
申请号：US16261578
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Ta-Wei Chiu , Chia-Lung Chang , Po-Chun Chen , Hong-Yi Fang , Yi-Wei Chen
IPC: H01L21/3105 , H01L21/027 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L27/108 , H01L29/66
Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
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公开(公告)号：US10804365B2
公开(公告)日：2020-10-13
申请号：US15985730
申请日：2018-05-22
Inventor： Chun-Chieh Chiu , Pin-Hong Chen , Yi-Wei Chen , Tsun-Min Cheng , Chih-Chien Liu , Tzu-Chieh Chen , Chih-Chieh Tsai , Kai-Jiun Chang , Yi-An Huang , Chia-Chen Wu , Tzu-Hao Liu
IPC: H01L21/02 , H01L29/49 , H01L27/108 , H01L21/3213 , H01L21/28 , H01L29/423 , H01L21/285
Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
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Patent Agency Ranking
公开(公告)号：US10707214B2
公开(公告)日：2020-07-07
申请号：US15990837
申请日：2018-05-29
Inventor： Chia-Chen Wu , Yi-Wei Chen , Chi-Mao Hsu , Kai-Jiun Chang , Chih-Chieh Tsai , Pin-Hong Chen , Tsun-Min Cheng , Yi-An Huang
IPC: H01L27/108 , C23C14/06 , C23C14/34 , C23C14/58 , H01L21/285
Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
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77.发明授权公开(公告)号：US10672774B2
公开(公告)日：2020-06-02
申请号：US15900800
申请日：2018-02-21
Inventor： Yi-Wei Chen , Pin-Hong Chen , Tsun-Min Cheng , Chun-Chieh Chiu
IPC: H01L27/108 , H01L21/285 , H01L21/3215 , H01L23/532
Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
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公开(公告)号：US20190318933A1
公开(公告)日：2019-10-17
申请号：US15986797
申请日：2018-05-22
Inventor： Tzu-Hao Liu , Yi-Wei Chen , Tsun-Min Cheng , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Po-Chih Wu , Pin-Hong Chen , Chun-Chieh Chiu , Tzu-Chieh Chen , Chih-Chien Liu , Chih-Chieh Tsai , Ji-Min Lin
IPC: H01L21/28 , H01L27/108 , G11C11/4097
Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
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公开(公告)号：US20190280095A1
公开(公告)日：2019-09-12
申请号：US15943717
申请日：2018-04-03
Inventor： Po-Chun Chen , Chia-Lung Chang , Yi-Wei Chen , Wei-Hsin Liu , Han-Yung Tsai
IPC: H01L29/423 , H01L21/762 , H01L27/108 , H01L21/28
Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
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公开(公告)号：US10340278B1
公开(公告)日：2019-07-02
申请号：US15885729
申请日：2018-01-31
Inventor： Wei-Hsin Liu , Cheng-Hsu Huang , Jui-Min Lee , Yi-Wei Chen
IPC: H01L23/48 , H01L27/108 , H01L23/528 , H01L21/3205 , H01L21/768 , H01L21/285 , H01L23/532
CPC classification number: H01L27/10894 , H01L21/28556 , H01L21/32053 , H01L21/32055 , H01L21/7685 , H01L21/76856 , H01L21/76864 , H01L21/76879 , H01L23/528 , H01L23/53266 , H01L23/53271 , H01L23/5329 , H01L27/10823 , H01L27/10885 , H01L27/10888 , H01L27/10897
Abstract: A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.
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