公开(公告)号：US07449410B2

公开(公告)日：2008-11-11

申请号：US11195174

申请日：2005-08-02

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L29/45

CPC classification number: H01L29/665 ,  H01L21/28518

Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括形成CoSi 2 N的方法，形成场效应晶体管的方法以及形成导电触点的方法。 在一个实施方案中，形成CoSi 2 N的方法包括在含硅衬底上形成包含MSi xSX的基本上非晶层，其中“M”包括至少一些金属其他 比钴。 包含钴的层被沉积在基本上无定形的MSi x x-xml集成层上。 将衬底退火有效地将含钴层的钴扩散通过基本上无定形的含杂质层并与含硅衬底的硅组合以形成CoSi 2 在基本无定形的MSi x x-xml集成层之下。 考虑了其他方面和实现。

公开(公告)号：US07030014B2

公开(公告)日：2006-04-18

申请号：US10885933

申请日：2004-07-06

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L21/44

CPC classification number: H01L21/28052 ,  H01L21/28061 ,  H01L27/10882 ,  H01L29/7833

Abstract: The invention includes methods of forming metal silicide having bulk resistance of less than 30 micro-ohms-centimeter. The metal of the metal silicide can be selected from Groups 3, 4, 8, 9 and 10 of the periodic table, with an exemplary metal being titanium. An exemplary method includes forming a titanium-containing layer directly against tantalum silicide. After the titanium-containing layer is formed directly against the tantalum silicide, titanium of the titanium-containing layer is converted to titanium silicide. Constructions formed in accordance with methodology of the present invention can be incorporated into circuitry associated with semiconductor devices, such as, for example, wordlines and bitlines.

Abstract translation: 本发明包括形成体积电阻小于30微欧姆·厘米的金属硅化物的方法。 金属硅化物的金属可以选自周期表的第3,4,8,9和10族，其中示例性的金属是钛。 一种示例性的方法包括直接与硅化钽形成含钛层。 在直接与硅化钽形成含钛层之后，将含钛层的钛转化为硅化钛。 根据本发明的方法形成的结构可以结合到与半导体器件相关的电路中，例如字线和位线。

公开(公告)号：US06783694B1

公开(公告)日：2004-08-31

申请号：US09560268

申请日：2000-04-26

Applicant: Whonchee Lee ,  Yongjun Jeff Hu

Inventor： Whonchee Lee ,  Yongjun Jeff Hu

IPC: C09K1300

CPC classification number: C23F1/28 ,  H01L21/32134 ,  H01L21/76895

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide. An etching composition including a mineral acid and a peroxide, preferably, HCl and hydrogen peroxide, is also described. The etching methods and compositions may be used in forming structures such as word lines, gate electrodes, local interconnects, etc.

Abstract translation: 用于集成电路制造的蚀刻方法包括在衬底组件上提供金属氮化物层，在金属氮化物层的第一部分上提供钴硅化物的区域，以及在金属氮化物层的第二部分上提供钴区域。 用至少一种包含无机酸和过氧化物的溶液除去钴的区域和金属氮化物层的第二部分。 无机酸可以选自HCl，H 2 SO 4，H 3 PO 4，HNO 3和稀HF（优选无机酸是HCl），并且过氧化物可以是过氧化氢。 此外，除去钴的区域和金属氮化物层的第二部分可以包括一步法或两步法。 在一步法中，用包含无机酸和过氧化物的单一溶液除去钴的区域和金属氮化物层的第二部分。 在两步法中，用含有无机酸和过氧化物的第一溶液除去钴的区域，并用含有过氧化物的第二溶液除去金属氮化物层的第二部分。 还描述了包含无机酸和过氧化物，优选HCl和过氧化氢的蚀刻组合物。 蚀刻方法和组合物可以用于形成诸如字线，栅电极，局部互连等的结构。

公开(公告)号：US06596595B1

公开(公告)日：2003-07-22

申请号：US09620442

申请日：2000-07-20

Applicant: Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

Inventor： Ronald A. Weimer ,  Yongjun Jeff Hu ,  Pai Hung Pan ,  Deepa Ratakonda ,  James Beck ,  Randhir P. S. Thakur

IPC: H01L21336

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/2807 ,  H01L21/32105

Abstract: A conductive structure for use in a semiconductor device includes a multilayer structure. A first layer includes a material containing silicon, e.g., polysilicon and silicon germanide. A barrier layer is formed over the first layer, with the barrier layer including metal silicide or metal silicide nitride. A top conductive layer is formed over the barrier layer. The top conductive layer can include metal or metal silicide. Selective oxidation can be performed to reduce the amount of oxidation of selected materials in a structure containing multiple layers, such as the multi-layer conductive structure. The selective oxidation is performed in a single-wafer rapid thermal processing system, in which a selected ambient, including hydrogen, is used to ensure low oxidation of a selected material, such as tungsten or a metal nitride.

Abstract translation: 用于半导体器件的导电结构包括多层结构。 第一层包括含硅的材料，例如多晶硅和锗锗。 在第一层上形成阻挡层，阻挡层包括金属硅化物或金属硅化物氮化物。 在阻挡层上形成顶部导电层。 顶部导电层可以包括金属或金属硅化物。 可以进行选择性氧化以减少包含多层结构的结构中所选材料的氧化量，例如多层导电结构。 选择性氧化在单晶片快速热处理系统中进行，其中使用包括氢的所选择的环境来确保所选择的材料如钨或金属氮化物的低氧化。

公开(公告)号：US06583038B2

公开(公告)日：2003-06-24

申请号：US10079404

申请日：2002-02-22

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L2144

CPC classification number: H01L27/10873 ,  H01L21/28061 ,  H01L27/10888 ,  H01L29/4941 ,  H01L29/665

Abstract: A polycide structure for use in an integrated circuit comprises a silicon layer; a barrier layer comprising ZSix where x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum; and a metal silicide layer, preferably cobalt silicide. The structure is particularly useful in applications requiring high temperature processing. The structure may be used as a gate stack, especially in memory applications such as DRAM. The structure provides thermal stability, thus avoiding agglomeration problems associated with high temperature processing combined with low resistivity.

公开(公告)号：US06458699B1

公开(公告)日：2002-10-01

申请号：US09843116

申请日：2001-04-24

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

IPC: H01L2144

CPC classification number: H01L29/41783 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76879 ,  H01L29/41775 ,  H01L29/7834

Abstract: A method of forming a contact to a substrate includes forming insulating material comprising a substantially amorphous outer surface over a substrate node location. A contact opening is etched through the insulating material over the node location. The node location comprises an outwardly exposed substantially crystalline metal silicide surface. The substrate with outwardly exposed substantially crystalline metal silicide node location surface is provided within a chemical vapor deposition reactor. A gaseous precursor including silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the outwardly exposed substantially crystalline metal silicide node location surface and not on the insulating material.

Abstract translation: 形成与衬底的接触的方法包括形成在衬底节点位置上包括基本无定形的外表面的绝缘材料。 通过节点位置处的绝缘材料蚀刻接触开口。 节点位置包括向外暴露的基本上结晶的金属硅化物表面。 具有向外暴露的基本上结晶的金属硅化物结点位置表面的衬底设置在化学气相沉积反应器内。 包括硅的气体前体在有效地基本上选择性地在多晶硅上沉积在外露的基本上结晶的金属硅化物结点位置表面而不是绝缘材料上的条件下被供给到化学气相沉积反应器。

公开(公告)号：US06426291B1

公开(公告)日：2002-07-30

申请号：US09653423

申请日：2000-08-31

Applicant: Yongjun Jeff Hu ,  Li Li

Inventor： Yongjun Jeff Hu ,  Li Li

IPC: H01L2144

CPC classification number: H01L21/2885 ,  H01L21/2257 ,  H01L21/28518 ,  H01L21/288

Abstract: A method of forming ultra-shallow source/drain junctions in MOS devices by co-depositing cobalt or nickel with an n or p-type dopant following a seeding step. The co-deposition of cobalt or nickel with the dopant is done either via an electroless or an electrodeposition. The co-deposited Co(P) or Ni(P) is capped with a layer of PVD elemental titanium. The wafer is then annealed such that the titanium partially alloys with the cobalt or nickel and getters some of the cobalt or nickel limiting the thickness of the cobalt or nickel salicide which forms over exposed regions of the silicon substrate. The excess metal layers are removed with a wet etch, such as a piranha etch. A subsequent drive step forms ultra-shallow source/drain junctions using the doped cobalt or nickel salicide as a diffusion source.

Abstract translation: 通过在接种步骤后与n或p型掺杂剂共沉积钴或镍，在MOS器件中形成超浅源极/漏极结的方法。 钴或镍与掺杂剂的共沉积可以通过无电解或电沉积来进行。 共沉积的Co（P）或Ni（P）被一层PVD元素钛覆盖。 然后将晶片退火，使得钛部分地与钴或镍合金并吸收一些钴或镍，限制了在硅衬底的暴露区域上形成的钴或镍自对准硅的厚度。 多余的金属层通过湿蚀刻（例如食人鱼蚀刻）去除。 随后的驱动步骤使用掺杂的钴或镍硅化物作为扩散源形成超浅源/漏结。

公开(公告)号：US06368962B2

公开(公告)日：2002-04-09

申请号：US09827973

申请日：2001-04-05

Applicant: Yongjun Jeff Hu ,  Pai-Hung Pan ,  Scott Jeffrey DeBoer

Inventor： Yongjun Jeff Hu ,  Pai-Hung Pan ,  Scott Jeffrey DeBoer

IPC: H01L4900

CPC classification number: H01L27/10885 ,  H01L21/76838 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10888

Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry. In one implementation, the invention comprises buried bit line memory circuitry fabricated by is the above and other methods.

Abstract translation: 本发明包括掩埋位线存储器电路，形成掩埋位线存储器电路的方法以及形成导线的半导体处理方法。 在一个实施方式中，形成导线的半导体处理方法包括在衬底上形成包含硅的区域。 包含TiNx的层沉积在包含硅的区域上，其中“x”大于0且小于1.含TiNx的层在含氮气氛中退火，有效地将TiNx层的至少最外部分转化为 硅包含到TiN的区域。 在退火之后，将元素钨包含层沉积在TiN上，并且至少含有元素的钨包含层，TiN和任何剩余的TiN x层被图案化成导电线。 在一个实现中，在制造掩埋位线存储器电路中使用诸如上述的方法。 在一个实施方案中，本发明包括通过上述和其它方法制造的掩埋位线存储电路。

公开(公告)号：US06337274B1

公开(公告)日：2002-01-08

申请号：US09454536

申请日：1999-12-06

Applicant: Yongjun Jeff Hu ,  Pai-Hung Pan ,  Scott Jeffrey DeBoer

Inventor： Yongjun Jeff Hu ,  Pai-Hung Pan ,  Scott Jeffrey DeBoer

IPC: H01L2144

CPC classification number: H01L27/10885 ,  H01L21/76838 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10888

Abstract: The invention includes buried bit line memory circuitry, methods of forming buried bit line memory circuitry, and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen containing atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer is deposited on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry. In one implementation, the invention comprises buried bit line memory circuitry fabricated by the above and other methods.

Abstract translation: 本发明包括掩埋位线存储器电路，形成掩埋位线存储器电路的方法以及形成导线的半导体处理方法。 在一个实施方式中，形成导线的半导体处理方法包括在衬底上形成包含硅的区域。 包含TiNx的层沉积在包含硅的区域上，其中“x”大于0且小于1.含TiNx的层在含氮气氛中退火，有效地将TiNx层的至少最外部分转化为 硅包含到TiN的区域。 在退火之后，将元素钨包含层沉积在TiN上，并且至少含有元素的钨包含层，TiN和任何剩余的TiN x层被图案化成导电线。 在一个实现中，在制造掩埋位线存储器电路中使用诸如上述的方法。 在一个实施方式中，本发明包括通过上述方法和其它方法制造的掩埋位线存储电路。

公开(公告)号：US06194315B1

公开(公告)日：2001-02-27

申请号：US09293212

申请日：1999-04-16

Applicant: Yongjun Jeff Hu ,  Li Li

Inventor： Yongjun Jeff Hu ,  Li Li

IPC: H01L2144

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868

Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.