公开(公告)号：US20240420024A1

公开(公告)日：2024-12-19

申请号：US18657414

申请日：2024-05-07

Applicant: STMicroelectronics International N.V.

Inventor： He Huang

IPC: G06N20/00

Abstract: A method for creating a classification model includes: obtaining at least one group of initial time-series signals associated with at least one initial acquisition parameter, creating at least one group of simulated time-series signals from the at least one group of initial time-series signals, creating various test classification models, from groups of initial or simulated time-series signals, assessing the performances of each test classification model, obtaining at least one group of final time-series signals associated with at least one final acquisition parameter, and creating the classification model.

公开(公告)号：US20240419201A1

公开(公告)日：2024-12-19

申请号：US18335797

申请日：2023-06-15

Applicant: STMicroelectronics International N.V.

Inventor： Lukas Buryanec

IPC: G05F1/575 ,  G05F1/46 ,  G05F1/573

Abstract: A voltage regulator circuit includes an input configured to receive an input voltage, an output configured to produce a regulated output voltage, a pass element coupled between the input and the output, a bypass element coupled in parallel with the pass element, a feedback divider coupled between the output and a ground node, an error amplifier coupled between a control node of the pass element and the feedback divider, and a dropout transition control circuit coupled to the feedback divider configured to activate a dropout mode of the voltage regulator circuit by controlling a dropout transition at the output from the regulated output voltage to a dropout voltage level to limit inrush current. The feedback divider is configured to produce a feedback signal indicative of the output voltage. The error amplifier is configured to minimize the difference between a reference and the feedback signal.

公开(公告)号：US12169060B1

公开(公告)日：2024-12-17

申请号：US18543303

申请日：2023-12-18

Applicant: STMicroelectronics International N.V.

Inventor： Jiongdi Jiang ,  Hui Yan ,  Qiaoyong Liu

IPC: F21V23/00 ,  F21V19/00 ,  F21Y115/10

Abstract: An example apparatus, an automotive lighting system, and an automotive lighting apparatus for driving a lighting element in an automotive lighting system are provided. The example apparatus includes a lighting element and a lighting element driver electrically connected to the lighting element and a serial communication bus. The lighting element driver includes a flexible circuit board, a serial communication interface configured to receive a serial communication message related to the lighting element, a power supply interface electrically connected to a power source, and a lighting element driver processor mounted on and electrically connected to the flexible circuit board. The lighting element driver transmits power from the power supply interface to the lighting element based at least in part on the serial communication message.

公开(公告)号：US20240413043A1

公开(公告)日：2024-12-12

申请号：US18207918

申请日：2023-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  Laurent Schwartz ,  Ludovic Fourneaud

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367

Abstract: Systems, apparatuses, and method for nanowires for semiconductor packages are provided herein. The semiconductor package may include die attached to a substrate. A lid may also be attached to the substrate. The die includes die nanowires and the lid includes lid nanowires. The nanowires may be formed over the entirety of the die or in a pattern. The lid may have a corresponding or symmetrical coverage or pattern. In the semiconductor package, the die nanowires and the lid nanowires are coupled to, among other things, provide improved heat dissipation.

公开(公告)号：US20240410993A1

公开(公告)日：2024-12-12

申请号：US18330914

申请日：2023-06-07

Applicant: STMicroelectronics International N.V.

Inventor： Alessandro NICOLOSI ,  Andrea GAMBERO ,  Juri GIOVANNONE

IPC: G01S7/4865 ,  G01S17/10 ,  G01S17/894

Abstract: An electronic system and method for generating a pulsed illumination signal in a multi-channel LIDAR application is provided. An example electronic system includes a pulsed signal generator, a pulse emitting circuit, and an illumination source. The pulsed signal generator includes a main switch, a selection switch controlling the flow of current to the illumination source, and a switching control circuit. The switching control circuit configured to receive an illumination source enabled signal indicating a difference between a duration of the illumination source enabled signal and a target duration of the illumination source enabled signal. The switching control circuit is configured to receive the duration target code and determine a main switch enable signal configured to activate the main switch and a selection switch enable signal configured to activate the selection switch, based at least in part on the duration target code and a target overlap.

公开(公告)号：US20240406163A1

公开(公告)日：2024-12-05

申请号：US18678831

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy ,  Maxime Mere ,  Frédéric Jouault

IPC: H04L9/40 ,  G06F21/10 ,  H04L9/32

Abstract: A method for life cycle management of a system-on-chip having functions includes multi-user ownership management listing owners of the functions in a directory, and allocating rights of a function over the life cycle of the system-on-chip, according to a configuration command including identifying the function, identifying a right of ownership or access to the function, and a signature of the owner of the function.

公开(公告)号：US20240405111A1

公开(公告)日：2024-12-05

申请号：US18204009

申请日：2023-05-31

Applicant: STMicroelectronics International N.V.

Inventor： Christophe MAURIAC ,  Laurent SIEGERT

IPC: H01L29/747

Abstract: A TRIAC features first and second main-terminal contacts, and a gate terminal contact, with multiple semiconductor regions stacked along a first-axis and extending laterally along an intersecting second-axis that defines first, second, and middle regions. The semiconductor regions include a third N-type region overlying the second main-terminal contact, a second P-type region overlying the second main-terminal contact, a second N-type region overlying the second P-type region, a first P-type region overlying the second N-type region, a first N-type region partially overlying the first P-type region, a fourth N-type region partially overlying the first P-type region, and a fifth N-type region partially overlying the first P-type region. The first main-terminal contact is partly on the first N-type region in the first region and on the first P-type region in the second region, while the gate terminal contact is partly on both the first P-type region and the fourth N-type region.

公开(公告)号：US20240405098A1

公开(公告)日：2024-12-05

申请号：US18623604

申请日：2024-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

公开(公告)号：US20240404940A1

公开(公告)日：2024-12-05

申请号：US18678025

申请日：2024-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Pascal CHEVALIER

IPC: H01L23/498 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735

Abstract: A device includes a bipolar transistor. The bipolar transistor includes: a collector region, a base region, and an emitter region. A first metallization is in contact with the emitter region, a second metallization is in contact with the base region, and a third metallization is in contact with the collector region. A first connection element is coupled to the first metallization and has dimensions, in a plane of the interface between the first metallization and the connection element, greater than dimensions of the first metallization. A second connection element is coupled to the second metallization and passes through spacers, which at least partially cover the second metallization, surrounding the emitter region. A third connection element is coupled to the third metallization and passes through spacers, which at least partially cover the third metallization, surrounding the base region.

公开(公告)号：US20240404569A1

公开(公告)日：2024-12-05

申请号：US18675916

申请日：2024-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Riccardo ZURLA

IPC: G11C7/16 ,  G06F7/544 ,  G11C11/54 ,  G11C13/00

Abstract: An in-memory computation (IMC) device is configured to receive input data and provide intermediate output data. A word line activation circuit receives input data and provides corresponding word line activation signals. A memory array includes memory cells in a matrix arrangement coupled to bit lines and to word lines. Each bit line is traversed by a respective bit line current depending on the memory cells connected to the bit line. Selectors each coupled to a respective part of the bit lines are configured to select one of the respective bit lines. A digital detector for each selector is electrically connected, through the respective selector, with the respective bit line selected. The digital detectors sample the respective bit line currents and, in response to the bit line currents, provide the respective intermediate output data.