公开(公告)号：EP0979524A1

公开(公告)日：2000-02-16

申请号：EP98914286.4

申请日：1998-03-24

Applicant: Candescent Technologies Corporation

Inventor： LEARN, Arthur, J. ,  HAVEN, Duane, A.

IPC: H01J5/00 ,  H01J17/49

CPC classification number: H01J31/127 ,  H01J29/90 ,  H01J2329/90

Abstract: A flat-panel display (100) including a substrate (102), a viewing screen (104), a non-conductive ring (106), many row conductive electrodes (120), conductive pads (122) and column buses (130). The ring vacuum-seals a cavity (108) between the substrate and the viewing screen. Coupled to one surface of the substrate, the row conductive electrodes have a conductivity that is higher than the conductive pads. Each pad is connected to one row electrode, and each pad extends through the ring to allow electrical coupling to its corresponding row electrode from outside the cavity while vacuum is maintained inside the cavity. The row electrodes are substantially parallel to each other, and are substantially perpendicular to the column buses. The conductive electrodes are protected from exposure to the ring. In one embodiment, the ring is a frit seal (106), the row conductive electrodes are made of aluminum, and the column buses and the pads are made of chromium.

公开(公告)号：EP0974162A1

公开(公告)日：2000-01-26

申请号：EP98914287.2

申请日：1998-03-24

Applicant: Candescent Technologies Corporation

Inventor： RAMANI, Swayambu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49866 ,  H01J29/88 ,  H01J2211/225 ,  H01J2329/00 ,  H01L23/498 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film coupled to a substrate includes a first layer (102) which is doped with nitrogen and a second layer (104) which is not doped with nitrogen. Both layers are made of the same material, which is either a transition or a refractory metal. The invention improves stress levels in these layers.

公开(公告)号：EP0968509A1

公开(公告)日：2000-01-05

申请号：EP98911427.7

申请日：1998-03-23

Applicant: Candescent Technologies Corporation ,  ADVANCED TECHNOLOGY MATERIALS, INC.

Inventor： XU, Xueping ,  BRANDES, George, R. ,  SPINDT, Christopher, J. ,  STANNERS, Colin, D. ,  MACAULAY, John, M.

IPC: H01J1/30 ,  H01J19/24

CPC classification number: H01J1/3042 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2329/00

Abstract: A cathode structure (200, 203, 204) suitable for a flat panel display is provided with coated emitters (229, 239, 230). The emitters are formed with material, typically nickel, capable of growing to a high aspect ration. These emitters are then coated with carbon containing material (240, 241) for improving the chemical robustness and reducing the work function. One coating process is a DC plasma deposition process in which acetylene is pumped through a DC plasma reactor (301, 305, 313, and 315) to create a DC plasma for coating the cathode structure. An alternative coating process is to electrically deposit raw carbon-based material onto the surface of the emitters, and subsequently reduce the raw carbon-based material to the carbon containing material. Work function of coated emitters is typically reduced by about 0.8 to 1.0 eV.

Abstract translation: 适用于平板显示器的阴极结构（200,203,204）设置有涂层发射器（229,239,230）。 发射体由能够生长到高纵横比的材料形成，典型地为镍。 然后用含碳材料（240,241）涂覆这些发射体，以提高化学稳定性并降低功函数。 一种涂覆工艺是DC等离子体沉积工艺，其中乙炔被泵送通过DC等离子体反应器（301,305,313和315）以产生用于涂覆阴极结构的DC等离子体。 替代的涂覆工艺是将原始的基于碳的材料电沉积到发射器的表面上，并随后将原始的基于碳的材料还原为含有碳的材料。 涂覆发射体的功函数通常降低约0.8至1.0eV。

公开(公告)号：EP1632927A2

公开(公告)日：2006-03-08

申请号：EP05024848.3

申请日：1999-07-08

Applicant: Candescent Technologies Corporation

Inventor： Elloway, Donald J. ,  Morris, David L. ,  Scannell, William J. ,  Spindt, Chistopher J.

IPC: G09G3/22 ,  H01J9/44

CPC classification number: G09G3/22 ,  G09G2310/06 ,  G09G2310/066 ,  G09G2330/02 ,  H01J9/39 ,  H01J9/44 ,  H01J31/127 ,  H01J2209/0223

Abstract: A method of removing contaminant particles in newly fabricated filed emission displays. Contaminant particles are removed by a conditioning process which includes the steps of: a)driving an anode (20) of a field emission display (FED) to a predetermined voltage; b) slowly increasing an emission current of the FED after the anode has reached the predetermined voltage; and c) providing an ion-trapping device for catching the ions and particles knocked off, or otherwise released, by emitted electrons (40). By driving the anode to the predetermined voltage and by slowly increasing the emission current of the FED, contaminant particles are effectively removed without damaging the FED. A method of operating FEDs is also provided to prevent gate-to-emitter current during turn-on and turn-off, which comprises the steps of: a) enabling the anode display screen (20); and b) enabling the electron-emitters (40) after the anode display screen is enabled. By allowing sufficient time for the anode display screen to reach a predetermined voltage before the emitter is enabled, the emitted electrons (40) will be attracted to the anode (20).

Abstract translation: 一种在新制造的场发射显示器中去除污染物颗粒的方法。 污染物颗粒通过调节过程去除，其包括以下步骤：a）将场致发射显示器（FED）的阳极（20）驱动到预定电压; b）在阳极达到预定电压后缓慢增加FED的发射电流; 以及c）提供离子捕获装置，用于捕获被发射的电子（40）敲除或以其它方式释放的离子和颗粒。 通过将阳极驱动到预定电压并通过缓慢增加FED的发射电流，有效地去除污染物颗粒而不损害FED。 还提供了一种操作FED的方法，以防止在导通和关断期间的栅极 - 发射极电流，其包括以下步骤：a）启用阳极显示屏幕（20）; 以及b）在使能阳极显示屏幕之后启用电子发射器（40）。 通过在发射极使能之前允许阳极显示屏足够的时间达到预定电压，发射的电子（40）将被吸引到阳极（20）。

公开(公告)号：EP1305812A2

公开(公告)日：2003-05-02

申请号：EP01935173.3

申请日：2001-05-09

Applicant: Candescent Technologies Corporation

Inventor： PORTER, John, D. ,  MACKEY, Bob, L. ,  NEIMEYER, Robert, G. ,  SPINDT, Christopher, J. ,  CHANG, David, C. ,  SAHLSTROM, Kris, E.

IPC: H01J29/00

CPC classification number: H01J29/028 ,  H01J29/864 ,  H01J2329/00 ,  H01J2329/863

Abstract: A multi-level matrix structure for retaining a support structure within a flat panel display device. In one embodiment, the multi-level matrix structure is comprised of a first parallel ridges. The multi-level matrix structure further includes a second parallel ridges. The second parallel ridges are oriented substantially orthogonally with respect to the first parallel ridges. In this embodiment, the second parallel ridges have a height which is greater than the height of the first parallel ridges. Furthermore, in this embodiment, the second plurality of parallel spaced apart ridges include contact portions for retaining a support structure at a desired location within a flat panel display device. Hence, when a support structure is inserted between at least two of the contact portions of the multi-level support structure, the support structure is retained in place, at a desired location within the flat panel display device, by the contact portions.

公开(公告)号：EP1110199A1

公开(公告)日：2001-06-27

申请号：EP99928822.8

申请日：1999-06-21

Applicant: Candescent Technologies Corporation

Inventor： MACKEY, Bob, L.

IPC: G09G3/22

CPC classification number: H01J9/227

Abstract: A method for fabricating a pixel assembly (315) on a faceplate of a display device, such as a field-emission display device. In one embodiment of the present invention, an application device (440) is aligned over a pixel assembly on the faceplate. The present invention dispenses a specific amount of a substance into the pixel assembly such that the substance is dispensed primarily into the pixel assembly and such that the substance is not substantially dispensed outside of the pixel assembly. The present invention dispenses the substance into the pixel assembly such that the substance is not dispensed on a top surface of a matrix structure (310), where the matrix structure separates rows and columns of adjacent pixel assemblies. In one embodiment, the substance is dispensed into the pixel assembly from a printer head (e.g., an ink-jet printer head) adapted to dispense the substance. The substance is selected from a group consisting of: a color filter material, a phosphor material, a wetting material, a lacquer material, and a reflective layer material.

公开(公告)号：EP1066618A1

公开(公告)日：2001-01-10

申请号：EP98960800.5

申请日：1998-12-07

Applicant: Candescent Technologies Corporation

Inventor： HANSEN, Ronald, L. ,  FRIEDMAN, Jay ,  STOIAN, Lee

IPC: G09G3/32

CPC classification number: G09G3/22 ,  G09G3/2011 ,  G09G2310/027 ,  G09G2320/043 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2320/0666

Abstract: A circuit for time multiplexing a voltage signal for controlling the color balance of a flat panel display (200). Within an FED screen, a matrix of rows (230) and columns (250) is provided and emitters are situated within each row-column intersection (100). Rows are sequentially activated during 'row on-time windows' by row drivers (220) and corresponding individual gray scale information (voltages) are driven over the columns by column drivers (240). Within each column driver, the present invention provides selection circuitry for driving a first voltage signal during a first part of the row on-time window and a second voltage during a second part of the row on-time window. The lengths of the first part and second part of the row on-time window can be adjusted for a given color, to adjust the color balance with respect to color.

Abstract translation: 一种用于时间多路复用电压信号以控制平板显示器（200）的色彩平衡的电路。 在FED屏幕内，提供行（230）和列（250）的矩阵，并且发射器位于每个行 - 列交叉点（100）内。 行驱动器（220）在“行开启时间窗”期间顺序地激活行，并且由列驱动器（240）在列上驱动对应的单独灰度级信息（电压）。 在每个列驱动器内，本发明提供用于在行导通时间窗的第一部分期间驱动第一电压信号的选择电路和在行导通时间窗的第二部分期间驱动第二电压的选择电路。 行准时窗口的第一部分和第二部分的长度可以针对给定的颜色进行调整，以调整相对于颜色的颜色平衡。

公开(公告)号：EP1055247A1

公开(公告)日：2000-11-29

申请号：EP99902333.6

申请日：1999-01-15

Applicant: Candescent Technologies Corporation

Inventor： SPINDT, Christopher, J. ,  FIELD, John, E.

IPC: H01J19/42 ,  H01J29/18

CPC classification number: H01J29/085 ,  H01J29/028 ,  H01J29/864 ,  H01J31/127 ,  H01J2201/025 ,  H01J2329/8625 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8655

Abstract: A flat panel display having a backplate structure (330), a faceplate structure (320), and a spacer (340) situated between the two plate structures is configured so that the electric potential field along the spacer approximates the potential field that would be present at the same location in free space, i.e., in the absence of the spacer, between the two plate structures. Consequently, the presence of the spacer does not significantly affect the trajectories of electrons moving from the backplate structure to the faceplate structures. Alternatively, the spacer is arranged to produce electron deflection that largely compensates for undesired electron deflection which occurs during earlier electron travel from the backplate structure to the faceplate structure. The net electron deflection is small.

公开(公告)号：EP1031129A1

公开(公告)日：2000-08-30

申请号：EP98937003.6

申请日：1998-07-23

Applicant: Candescent Technologies Corporation

Inventor： HANSEN, Ronald, L. ,  SPINDT, Christopher, J.

IPC: G09G3/00 ,  G09G3/10

CPC classification number: G09G3/22 ,  G09G2320/029 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2320/0606 ,  G09G2320/0626

Abstract: A method and apparatus to provide performance adjustments for FEDs during operation are provided. More specifically, the present invention provides two circuit embodiments for compensating for temperature induced brightness variations of the panel display. In a closed loop embodiment, a sample display circuit (501) that is substantially similar to a FED (300) being adjusted is used to generate a performance indicator signal which is compared against a reference signal to determine a difference signal. The difference signal is then used to adjust the operation performance of the FED as well as the sample display circuit. In an opened loop embodiment, a current source (609) generates a reference current across a sample resistor (603) which is made from the same material as the resistor layer (111) inside the FED's cathode (107). The voltage across the sample resistor is compared against a reference signal to determine a difference signal. The difference signal is then used to increase or decrease the brightness of the panel display, as needed, to compensate for temperature induced variations or other types of environment induced variations (e.g., humidity, aging, mild voltage drift that creates undesirable current drift, etc.) thereof.

公开(公告)号：EP1029337A1

公开(公告)日：2000-08-23

申请号：EP98936954.1

申请日：1998-07-21

Applicant: Candescent Technologies Corporation

Inventor： ELIZONDO, Philip, J. ,  CHAKRAVORTY, Kishore, K. ,  CAUDILLO, David

IPC: H01J9/02

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: A method for uniformly depositing polymer particles (800) onto the surface of a gate metal layer during the formation of a gate electrode. In one embodiment, the present invention comprises immersing a substrate (906) having a layer of a gate metal disposed over the surface thereof in a fluid bath (902) containing polymer particles. Additionally, in the present embodiment, the layer of gate metal disposed over the substrate has approximately the same thickness as a desired thickness of the gate electrode to be formed. Next, the present embodiment applies a uniform potential across the surface of the layer of gate metal such that the polymer particles (800) are uniformly deposited onto the layer of gate metal with a spatial density of approximately 100,000,000 to 1,000,000,000,000 particles per square centimeter. In the present embodiment the polymer particles adhere to the surface of the layer of gate metal via Van der Waal's forces and/or via a charge difference between each particle and the layer of gate metal. The present embodiment then removes the substrate having the layer of the gate metal and the particles deposited thereon from the fluid bath.