公开(公告)号：DE69409422D1

公开(公告)日：1998-05-14

申请号：DE69409422

申请日：1994-02-25

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： DORAN DANIEL B

IPC: B08B7/04 ,  B08B7/00 ,  H01L21/00 ,  H01L21/304 ,  H01L21/673 ,  B08B3/08

Abstract: A system and a method for washing objects, such as cassettes and carriers used to hold and transport silicon wafers during manufacture of semiconductor chips. The method employs the steps of exposing the objects to ultraviolet radiation in a process chamber, spraying of developer fluid onto the objects, rinsing the objects, spraying of surfactant solution onto the objects, rinsing the objects and drying the objects using heated, filtered and ionized ultra low particle air (ULPA)

公开(公告)号：DE69405442T2

公开(公告)日：1998-04-02

申请号：DE69405442

申请日：1994-03-17

Applicant: NCR INT INC ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： CRAFTS HAROLD S

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0175 ,  H03H7/38

Abstract: An I/O transceiver circuit, suitable for use on each integrated circuit of a multi-chip module, controls the output resistance of the transmitter portion (20). Control of the output resistance is achieved by a phase-locked-loop arrangement which includes a phase detector (102) a charge pump (106), a low-pass filter (108), a voltage controller (110) and a voltage controlled oscillator (120). Control of the output resistance allows operation without characteristically terminated I/O lines between multi-chip modules, thereby saving power otherwise wasted in the terminating resistors.

公开(公告)号：GB2312303A

公开(公告)日：1997-10-22

申请号：GB9713332

申请日：1995-12-29

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： OH JONG-HOON

IPC: G11C7/10 ,  G11C11/417 ,  G11C8/04 ,  G11C11/407 ,  G11C11/408 ,  H03K23/00 ,  H03K23/64 ,  H03K21/00

Abstract: A counter system has a first counter (1) seeded by several input signals and a second counter (2) seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interleaved count sequence or a sequential count sequence.

公开(公告)号：GB9716013D0

公开(公告)日：1997-10-01

申请号：GB9716013

申请日：1997-07-29

Applicant: HYUNDAI ELECTRONICS AMERICA

IPC: G06F12/14 ,  G06F12/08 ,  G06F21/24 ,  G06T1/20 ,  H04N5/907 ,  H04N7/26 ,  H04N7/50

Abstract: Computer systems may be provided with additional performance for demanding applications while adding little additional hardware. For example, a slave device for a host computer system combines an embedded programmable controller with non-volatile memory, local RAM, and interface logic. The host computer system treats the slave device as if it would be a hierarchical memory system such as a conventional disk drive on which it may store and retrieve files. Additionally, the host computer system may program the controller to perform operations on stored information, including image processing and/or data compression. The non-volatile memory may include a disk drive, writable CD-ROM, optical drive, or non-volatile solid state memory.

公开(公告)号：DE69123100T2

公开(公告)日：1997-06-12

申请号：DE69123100

申请日：1991-08-21

Applicant: AT & T GLOBAL INF SOLUTION ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC

Inventor： CRAFTS HAROLD S ,  WALDRON ROBERT D

IPC: H03K3/356 ,  H03K3/3562

Abstract: A high speed CMOS clocked D-type flip-flop circuit (200) includes a master section (210) having input terminals (201, 203) adapted to receive D and D/ inputs and having parallel output terminals (247, 249) coupled to inputs of a slave section (220) which provides Q and Q/ outputs on Q and Q/ flip-flop output terminals (205, 207). The master and slave sections (210, 220) each include four CMOS tristate inverters (212-218; 222-228). The provision of parallel data paths having a small number of gates therein enables high-speed flip-flop operation to be achieved. A clock generating circuit (230) which may be selectively enabled generates true and complementary clock signals for the flip-flop circuit (200). In a modification, provision is made for a RESET signal to reset the flip-flop circuit (200).

公开(公告)号：DE69120901T2

公开(公告)日：1997-03-06

申请号：DE69120901

申请日：1991-10-25

Applicant: AT & T GLOBAL INF SOLUTION ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC FORT COLLINS

Inventor： DUKES GLENN E

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/0175

公开(公告)号：DE19626427A1

公开(公告)日：1997-01-02

申请号：DE19626427

申请日：1996-07-01

Applicant: HYUNDAI ELECTRONICS IND ,  HYUNDAI ELECTRONICS AMERICA

Inventor： PRATER JAMES S

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L27/14 ,  H04N1/00 ,  H04N1/195 ,  H04N5/335 ,  H04N17/00 ,  H04N3/15

Abstract: A picture element sensor circuit in an image array scanner is tested by driving a reset FET with a controllable voltage to set the reverse-bias voltage across the photo-diode at any selectable level of test voltage. In this way each pixel sensor circuit in the array may be tested as if it had received a desired amount of illumination. Alternatively, the drive voltage for the reset transistor is provided over the column output line. The controllable test voltage can be applied to the column line when no row access enable signal is applied to the array. In this situation the column line source follower circuit is inhibited by the row access FETs. Thus, a separate test voltage can be driven onto the column line, through a reset switch, and connected through the pixel sensor reset transistor to the pixel sensor photo-diode. The variable reset voltage, that is driven onto the column line, can be varied between ground and the normal bias voltage VDD for the pixel sensor by use of parallel connected P-channel FET and N-channel FET.

公开(公告)号：DE69123100D1

公开(公告)日：1996-12-19

申请号：DE69123100

申请日：1991-08-21

Applicant: AT & T GLOBAL INF SOLUTION ,  HYUNDAI ELECTRONICS AMERICA ,  SYMBIOS LOGIC INC FORT COLLINS

Inventor： CRAFTS HAROLD S ,  WALDRON ROBERT D

IPC: H03K3/356 ,  H03K3/3562

Abstract: A high speed CMOS clocked D-type flip-flop circuit (200) includes a master section (210) having input terminals (201, 203) adapted to receive D and D/ inputs and having parallel output terminals (247, 249) coupled to inputs of a slave section (220) which provides Q and Q/ outputs on Q and Q/ flip-flop output terminals (205, 207). The master and slave sections (210, 220) each include four CMOS tristate inverters (212-218; 222-228). The provision of parallel data paths having a small number of gates therein enables high-speed flip-flop operation to be achieved. A clock generating circuit (230) which may be selectively enabled generates true and complementary clock signals for the flip-flop circuit (200). In a modification, provision is made for a RESET signal to reset the flip-flop circuit (200).

公开(公告)号：GB9617595D0

公开(公告)日：1996-10-02

申请号：GB9617595

申请日：1996-08-22

Applicant: HYUNDAI ELECTRONICS AMERICA ,  ODEUM MICROSYSTEMS INC

IPC: G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  H04N7/30

Abstract: A fast and efficient implementation of the inverse discrete cosine transform (IDCT). The disclosed IDCT processor achieves a good balance between efficient VLSI implementation and number of needed arithmetic operations and is thus particularly useful in real-time speech and video decompression applications. A standard IDCT computation is modified by factoring an IDCT formula into two parts: a prescaling of each input value followed by a multiplication with a matrix specially chosen so that the product will represent the IDCT of the input data. The premultiply constants are chosen so that the specially chosen matrix has a limited number of distinct values. The VLSI implementation of the matrix multiplication is thus greatly simplified.

公开(公告)号：DE4436555A1

公开(公告)日：1995-04-20

申请号：DE4436555

申请日：1994-10-13

Applicant: HYUNDAI ELECTRONICS AMERICA

Inventor： BLANKENBECKLER DAVE ,  WHITEHEAD FRANK R

IPC: G11B11/10 ,  G11B7/09 ,  G11B11/105 ,  G11B7/095

Abstract: A focus and tracking error detection system for an optical disk drive in which a light beam is reflected from the surface of an optical disk. The system includes a lens for directing the reflected light beam toward a first point and a prism disposed between the lens and the first point for diverting a portion of the reflected light beam toward a second point A first photodetector is disposed between the prism and the first point a first distance from the first point A second photodetector is spaced from the second point the same first distance and opposite the prism. The first photodetector has a first photosensitive region in a central portion thereof and a second and third photosensitive region on opposing sides of the first photosensitive region. The second photodetector has a fourth photosensitive region in the central portion thereof and a fifth and sixth photosensitive regions on opposing sides of the fourth photosensitive regions. A circuit is coupled to the first and second photodetectors. The circuit includes means for adding respectively the outputs of the second and third photosensitive regions and the outputs of the fifth and sixth photosensitive regions to produce first and second added signals. Means are also provided for normalizing respectively the first and second added signals relative to a total signal from the three photosensitive regions of the first and second photodetectors to produce a first and second normalized focus error signals.