公开(公告)号：US20040117553A1

公开(公告)日：2004-06-17

申请号：US10716456

申请日：2003-11-20

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Shigeo Kurakata ,  Kunihiro Katayama ,  Motoki Kanamori ,  Atsushi Shikata ,  Tetsuya Iida

IPC: G06F012/00

CPC classification number: G06K19/0701 ,  G06K19/07

Abstract: A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor. If the resistance value of the pull-up resistor of the select terminal is lowered at the time of mode determination, an adverse effect of the lowering of a potential by the pull-down resistor can be circumvented.

Abstract translation: 提供了一种存储卡，其中通过输入端的上拉电阻降低功耗，并且防止由主机设备的下拉电阻引起的误操作。 存储卡具有连接到上拉电阻的选择端子。 当基于来自选择端子的输入确定存储卡的模式时，在确定定时之前为选择端的上拉电阻选择相对较低的电阻值，并且将上拉电阻恢复到初始值 模式确定后的电阻值。 相对较高的电阻值减小了选择端子的上拉电阻消耗的漏电流。 当下拉电阻连接到与存储卡相连的存储卡主机的端子时，如果上拉电阻的电阻值过高，则会受到电流的影响 下拉电阻。 如果选择端子的上拉电阻的电阻值在模式确定时降低，则可以避免下拉电阻降低电位的不利影响。

公开(公告)号：US20040105324A1

公开(公告)日：2004-06-03

申请号：US10667512

申请日：2003-09-23

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Ryotaro Sakurai ,  Hitoshi Tanaka ,  Satoshi Noda ,  Koji Shigematsu

IPC: G11C007/00

CPC classification number: G11C16/3409 ,  G11C11/5621 ,  G11C16/225 ,  G11C16/30 ,  G11C16/3404

Abstract: An electrically programmable and erasable nonvolatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract translation: 电气可编程和可擦除的非易失性半导体存储器如闪存被设计成其中当在对非易失性存储器中使用的存储器单元执行写入或擦除操作的过程中发生电源的截止时， 半导体存储器，中断正在执行的操作，并且执行回写操作以改变存储单元在相反方向上的阈值电压。 此外，该配置还允许根据电源电压的电平来改变内部电源配置中的电荷泵级数，以使回写操作正确执行。 结果，即使在写入或擦除操作的过程中电源断开的情况下，也不会将存储器单元置于耗尽状态。

公开(公告)号：US20040100722A1

公开(公告)日：2004-05-27

申请号：US10691612

申请日：2003-10-24

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Yasuhiko Kokami

IPC: G11B021/02 ,  G11B015/46

CPC classification number: G11B5/5526 ,  G11B5/54 ,  G11B21/02

Abstract: The present invention provides a magnetic disk storage system including a spindle motor that rotates a magnetic disk, a spindle motor drive circuit that rotatably drives the spindle motor, a magnetic head that performs reading of information on the magnetic disk, a voice coil motor that moves the magnetic head, and a voice coil motor drive circuit that drives the voice coil motor. When the magnetic head is loaded from a standby position to the surface of the magnetic disk, the rotational speed of the spindle motor is made slower than a rotational speed at a normal operation. Upon power-off, the spindle motor drive circuit is caused to carry out a stepup converter operation to thereby generate a voltage higher than a back electromotive voltage, and causes a control circuit and a drive circuit to operate by the high voltage to thereby enable speed control at the movement of the magnetic head to a predetermined standby position.

Abstract translation: 本发明提供一种磁盘存储系统，包括：旋转磁盘的主轴电动机;可旋转地驱动主轴电动机的主轴电动机驱动电路;执行磁盘上的信息读取的磁头;移动的音圈电动机; 磁头和驱动音圈马达的音圈马达驱动电路。 当磁头从备用位置装载到磁盘表面时，主轴电动机的转速比正常操作时的转速慢。 断电时，使主轴电动机驱动电路进行升压转换器动作，从而产生高于反电动势电压的电压，使控制电路和驱动电路通过高电压进行动作， 控制磁头移动到预定待机位置。

公开(公告)号：US20040085800A1

公开(公告)日：2004-05-06

申请号：US10670532

申请日：2003-09-26

Applicant: Renesas Technology Corp ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Yutaka Ogawa ,  Kazutomo Ogura ,  Naofumi Satou ,  Kiyotada Funane

IPC: G11C011/22

CPC classification number: G11C11/417

Abstract: A semiconductor integrated circuit device provided with a SRAM realizing low power consumption and high speed is to be provided. Out of memory circuits which cause a timing generator circuit which selects writable and readable memory cells with the address selector circuit, conveys write signals to a memory cell selected by a write circuit, conveys read signals from a memory cell selected by a read circuit, and receives a clock signal, to generate operational timing signals to be conveyed to an address selector circuit, a write circuit and a read circuit, a circuit in which the operational timing is not too tight is configured of a higher threshold voltage MOSFET than the MOSFETs of other circuits.

Abstract translation: 提供具有实现低功耗和高速的SRAM的半导体集成电路器件。 导致定时发生器电路的存储器电路不足，其使用地址选择器电路选择可写入和可读存储器单元，将写入信号传送到由写入电路所选择的存储单元，传送来自读取电路选择的存储器单元的读取信号，以及 接收时钟信号，以产生要被传送到地址选择器电路，写入电路和读取电路的操作定时信号，其中操作时序不太紧的电路由比MOSFET高的阈值电压MOSFET 其他电路。

公开(公告)号：US20040070952A1

公开(公告)日：2004-04-15

申请号：US10676098

申请日：2003-10-02

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Akira Higuchi ,  Hirotaka Nishizawa ,  Junichiro Osako ,  Kenji Osawa

IPC: H05K001/14

CPC classification number: G06K19/07732 ,  G06K19/0719 ,  G06K19/07733 ,  G06K19/07741 ,  G06K19/07743 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0268 ,  H05K1/117 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An IC card and card adapters are designed so that the IC card of a specific standard (e.g., MMC standard) is compatible with IC cards and terminals of other standards (e.g., MS card standard and USB terminal standard). In the IC card (MMC), a controller IC, which is connected to a flash memory, includes a voltage pull-down detector, a mode controller, a USB-mode interface controller, a MS-mode interface controller, and an MMC/SD-mode interface controller. The card adapters suffice to have component parts which are easy in formation and low in cost such as wiring lines and resistors. The voltage pull-down detector of the IC card detects the voltage pull-down caused by the resistors, and the mode controller selects the USB-mode interface controller, MS-mode interface controller or MMC/SD-mode interface controller so that the IC card becomes compatible with the corresponding IC card standard.

Abstract translation: IC卡和卡适配器被设计成使得特定标准（例如，MMC标准）的IC卡与IC卡和其他标准的终端（例如，MS卡标准和USB终端标准）兼容。 在IC卡（MMC）中，连接到闪速存储器的控制器IC包括电压下拉检测器，模式控制器，USB模式接口控制器，MS模式接口控制器和MMC / SD模式接口控制器。 卡适配器足以具有易于形成的部件，成本低廉，例如布线和电阻器。 IC卡的电压下拉检测器检测由电阻引起的电压下拉，模式控制器选择USB模式接口控制器，MS模式接口控制器或MMC / SD模式接口控制器，使IC 卡与相应的IC卡标准兼容。

公开(公告)号：US20040065744A1

公开(公告)日：2004-04-08

申请号：US10667663

申请日：2003-09-23

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Atsushi Shiraishi ,  Takayuki Tamura ,  Chiaki Kumahara ,  Shinsuke Asari

IPC: G06K019/06

CPC classification number: G11C16/3418 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7207 ,  G11C16/349

Abstract: The present invention provides a memory card in which stored information is not lost undesirably even when an operation power source is shut down during an erasing/writing process. A nonvolatile memory has an erase table in which a free-space information flag is associated with each physical address of a memory area and an address translation table in which a physical address of a memory area is associated with each logical address. The free-space information flag indicates whether a corresponding memory area is permitted to be erased or not. A control circuit determines a memory area to which rewrite data is to be written by referring to the free-space information flag of the erase table, reflects the physical address and the logical address of the memory area to which the data is written into the address translation table, and updates the free-space information flag of the erase table. The memory area to which rewrite data is to be written is determined by referring to the free-space information flag of the erase table, and rewriting is not performed in the same memory area.

Abstract translation: 本发明提供一种存储卡，其中即使在擦除/写入处理期间操作电源被关闭时，存储信息也不会不期望地丢失。 非易失性存储器具有擦除表，其中空闲信息标志与存储区域的每个物理地址相关联，以及地址转换表，其中存储区域的物理地址与每个逻辑地址相关联。 自由空间信息标志指示是否允许擦除对应的存储区域。 控制电路通过参照擦除表的自由空间信息标志来确定要写入重写数据的存储器区域，将数据写入地址的存储区域的物理地址和逻辑地址反映 翻译表，并更新擦除表的空闲信息标志。 通过参照擦除表的自由空间信息标志确定要写入重写数据的存储区域，并且不在同一存储区域中进行重写。

公开(公告)号：US20040061550A1

公开(公告)日：2004-04-01

申请号：US10669304

申请日：2003-09-24

Applicant: Elpida Memory, Inc. ,  Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Yoji Idei ,  Yusuke Shimizu

IPC: G05F001/10

CPC classification number: G05F3/262

Abstract: The semiconductor device includes a first current mirror circuit combining analog power sources and digital power sources to receive small amplitude signals and constant-voltage input signals, a second current mirror circuit for receiving a signal output from the first current mirror circuit and for level-converting the signal from analog power source to digital power source, a first node provided in the first current mirror circuit, a second node provided in the second current mirror circuit, and an inverter circuit for receiving a signal output on the basis of the voltage levels of the first node and the second node and for outputting a CMOS level signal.

Abstract translation: 半导体器件包括组合模拟电源和数字电源以接收小振幅信号和恒压输入信号的第一电流镜电路，用于接收从第一电流镜电路输出的信号和用于电平转换的第二电流镜电路 从模拟电源到数字电源的信号，设置在第一电流镜电路中的第一节点，设置在第二电流镜电路中的第二节点，以及反相器电路，用于基于电压电平 第一节点和第二节点，并用于输出CMOS电平信号。

公开(公告)号：US20040041587A1

公开(公告)日：2004-03-04

申请号：US10647280

申请日：2003-08-26

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC: H03K019/0175

CPC classification number: H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

公开(公告)号：US20030228725A1

公开(公告)日：2003-12-11

申请号：US10452126

申请日：2003-06-03

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC: H01L021/336 ,  H01L021/8234

CPC classification number: H01L21/823857 ,  H01L21/823462

Abstract: A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film.

Abstract translation: 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且移除氮导入的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面。

公开(公告)号：US20030222283A1

公开(公告)日：2003-12-04

申请号：US10430319

申请日：2003-05-07

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

IPC: H01L031/0328

CPC classification number: G11C29/26 ,  G11C2029/1806 ,  G11C2029/2602 ,  G11C2029/3202

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract translation: 提供了多个桥接电路，其将来自连接到不同访问数据宽度的多个存储器的公共测试总线的测试数据信息和地址解码逻辑转换为每个存储器的固有访问数据宽度，并且还将测试地址信息 从公共测试总线到每个存储器的固有位格式，将结果提供给相应的存储器。 测试地址信息从公共测试总线并行提供给多个存储器以实现并行测试。 因此，测试数据信息可以并行地提供给不同数据宽度的多个存储器，并且用于测试地址信息的各个存储器中的地址扫描方向可以根据固有位格式被均匀化到特定方向。 因此，可以提高通过用于多个片上存储器的匹配模式的存储器测试效率。