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公开(公告)号：NL9201248A
公开(公告)日：1993-06-01
申请号：NL9201248
申请日：1992-07-10
Applicant: KOREA TELECOMMUNICATION
Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.
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公开(公告)号：GB2261350A
公开(公告)日：1993-05-12
申请号：GB9222756
申请日：1992-10-28
Applicant: KOREA TELECOMMUNICATION
Inventor： LEE CHONG RAK , PARK YONG KYE
Abstract: A speech synthesis system utilizes a periodic waveform decomposition and relocation method which is a coding method in which signals of voiced sound interval among original speech are decomposed into wavelets each of which corresponds to a speech waveform for one period made by each glottal pulse and the wavelets are respectively coded and stored. Then the wavelets nearest to the positions where the wavelets are to be located are selected from stored wavelets and decoded and superposed to each other such that original sound quality can be maintained and duration and pitch frequency of speech segment can be controlled.
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公开(公告)号：FR2683354A1
公开(公告)日：1993-05-07
申请号：FR9208505
申请日：1992-07-09
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.
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公开(公告)号：DE4222846A1
公开(公告)日：1993-05-06
申请号：DE4222846
申请日：1992-07-11
Inventor： VERZICHT DES ERFINDERS AUF NENNUNG
Abstract: A MOSFET controlling multiplier for obtaining the precise function of the operational multiplication by offsetting the offset voltage of MOSFET to remove the non-linear current of MOSFET, utilizing symmetrical voltage sources and a current mirror circuit is disclosed. The MOSFET controlling multiplier utilizes a MOSFET linear means for linearly varying the output current I to a node A in accordance with an input voltage from an input voltage source Vg and a symmetrical input voltage from voltage sources Vx and -Vx. The input voltage from the input voltage source Vg is operatively associated with the symmetrical input voltage from the voltage sources Vx and -Vx. An impedance element Z outputs a voltage Vo, with the impedance element Z being connected to the node A of the MOSFET linear means and the ground.
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公开(公告)号：GB9305529D0
公开(公告)日：1993-05-05
申请号：GB9305529
申请日：1993-03-17
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.
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Patent Agency Ranking
公开(公告)号：GB2261093A
公开(公告)日：1993-05-05
申请号：GB9213382
申请日：1992-06-24
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN IL SONG
Abstract: MOS circuit 1 yields a high-impedance output current i proportional to the product of Vg and the symmetrical input Vx, - Vx. M1 operates in the triode region with symmetrical source and drain potentials ensured by matched loads M4, M5. M2 mirrors the input leg current to the output node A, and PMOS M3 cancels the offset current due to finite V1 of M1. Load Z provides a voltage output, with optional M8 acting as a synapse. Input switches may be inserted (fig. 5).
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公开(公告)号：SE9201882L
公开(公告)日：1993-05-02
申请号：SE9201882
申请日：1992-06-18
Applicant: KOREA TELECOMMUNICATION
Inventor： HAN I S
Abstract: A MOSFET analog multiplier with a variable resistive MOSFET linear means for linearly varying output current I depending upon a symmetrical input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source V1 operatively associated with the symmetrical input voltage from the voltage source V2 and -V2, with the variable resistive MOSFET linear means having a node A to output the varied output current I therethrough is disclosed. An operational amplifying unit for amplifying the linearly varied output current I and which includes an operational amplifier U with an inverting input terminal connected to the node A of the MOSFET linear means, a non-inverting input terminal connected to ground, and an output terminal. The operational amplifying unit further includes a feedback element Z connected between the inverting input terminal and the output terminal of the operational amplifier U, where in use the output terminal outputs a voltage Vo.
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88.发明专利
公开(公告)号：LU88189A1
公开(公告)日：1993-04-15
申请号：LU88189
申请日：1992-11-06
Applicant: KOREA TELECOMMUNICATION
Inventor： LEE CHONG RAK
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公开(公告)号：DE3941252C2
公开(公告)日：1992-08-20
申请号：DE3941252
申请日：1989-12-14
Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, DAEJEON, KR , KOREA TELECOMMUNICATION AUTHORITY, SEOUL/SOUL, KR
Abstract: A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.
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