公开(公告)号：EP0194755A1

公开(公告)日：1986-09-17

申请号：EP86300958.5

申请日：1986-02-12

Applicant: PRIME COMPUTER, INC.

Inventor： Goodwin, Peter A.

IPC: G01R19/145

CPC classification number: G01R19/145

Abstract: 57 An apparatus and method for detecting an AC power failure condition employs a fast attack, slow decay, energy storage circuit (28) for tracking an AC input signal and for providing a slowly decaying output based upon a last received peak voltage input value. A current detection circuit (50) monitors the current flow to the storage circuit from the AC mains (72, 74) and generates a current detection signal in response thereto. A power failure condition is declared when either the voltage across the energy storage circuit decays below a selected threshold value or current is not detected flowing to the energy storage circuit at a selected time. A particular current detection circuit (200) employs a high permeability core (201) which is saturated by a current in the sensed line having a current value below an expected peak current flowing to the energy storage circuit. An interrogation pulse periodically energizes an interrogation winding which, in the absence of current in the sensed line, induces a signal across an output winding. When the current being sensed is sufficient to saturate the core, no output signal is generated across the output winding. Circuitry monitors the voltage across the output winding and generates a conditioning signal when even a selected minimum current is not detected in the line at the time of the interrogation pulse.

公开(公告)号：EP0134620A2

公开(公告)日：1985-03-20

申请号：EP84303073.5

申请日：1984-05-08

Applicant: PRIME COMPUTER, INC.

Inventor： Jones, Walter A. ,  Jones, Paul R., Jr. ,  Ardini, Joseph L., Jr. ,  Papworth, David B.

IPC: G06F9/38

CPC classification number: G06F9/3889 ,  G06F9/3867

Abstract: A data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory. The pipeline control unit can independently control the flow of instructions through the two pipelines. This is important for operation in conjunction with a microcode storage element which allows conditional branching and subroutine operation. Circuitry also detects pipeline collisions and exception conditions and delays or inhibits operation of one or more of the pipeline stages in response thereto. Under control of the pipeline control unit, one of the independent pipelines can operate while the other is halted. Further, a program . instruction flow prediction apparatus and method employ a high speed flow prediction storage element for predicting redirection of program flow prior to the time when the instruction has been decoded. Circuitry is further provided for updating the storage element, correcting erroneous branch and/or non-branch predictions, and accommodating instructions occurring on even or odd boundaries of the normally read double word instruction. Circuitry is further provided for updating the program flow in a single execution cycle so that no disruption to normal instruction sequencing occurs.

公开(公告)号：EP0220929A3

公开(公告)日：1989-09-13

申请号：EP86308201.2

申请日：1986-10-22

Applicant: PRIME COMPUTER, INC.

Inventor： Chan, Carl ,  Feustel, Edward A.

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F9/4843 ,  G06F12/08

Abstract: Methods and apparatus are described for implementing fork operations on UNIX or UNIX-emulating operating systems, particularly in multi-user environments. The invention reduces the copy time, the number of page faults and, consequently the input-output ("I/O") operations between the central processing ünit, main memory and auxilliary memory. In one aspect of the invention, fork operations are executed by redefining those pages of the parent process image resident in main memory as pages of a child process image and modifying the page maps accordingly. Page faults are thereby eliminated for pages located in auxiliary memory. Additional improvements in performance are obtained by monitoring the level of main memory utilization and selecting optimal procedures based on the amount of excess capacity in main memory.

公开(公告)号：EP0287295A2

公开(公告)日：1988-10-19

申请号：EP88303195.7

申请日：1988-04-11

Applicant: PRIME COMPUTER, INC.

Inventor： Presant, Stephen D.

IPC: G06F9/46 ,  G06F13/10

CPC classification number: G06F9/4881 ,  G06F9/5011 ,  G06F13/10 ,  G06F15/161

Abstract: A method for performing an input/output process containing a programmed input/output (PIO) instruction in a multiprocessor system including at least two processors each having an associated I/O bus with I/O devices connected thereto. The method comprises the steps of storing a unique address and a bus location for each I/O device in a device location table, determining the address of a referenced I/O device prior to performing the PIO instruction, reading the corresponding I/O bus location of the referenced I/O device from the device location table and executing the input/output process on the prescribed processor associated with the I/O bus to which the referenced I/O device is located. The method is used in conjunction with a task scheduler including a process control block for each scheduled process. When the PIO instruction references a device on the local I/O bus, the input/output process is executed normally. To execute the input/output process on a remote processor, a locked descriptor identifying the remote processor is placed in the process control block for that process. The input/output process is then scheduled for execution on the remote processor.

Abstract translation: 一种用于在包括至少两个处理器的多处理器系统中执行包含编程输入/输出（PIO）指令的输入/输出处理的方法，每个处理器具有与其连接的I / O设备的相关联的I / O总线。 该方法包括以下步骤：在设备位置表中存储每个I / O设备的唯一地址和总线位置，在执行PIO指令之前确定所引用的I / O设备的地址，读取相应的I / O总线 来自设备位置表的引用的I / O设备的位置，并且在与所引用的I / O设备所在的I / O总线相关联的规定处理器上执行输入/输出处理。 该方法与包括用于每个调度过程的过程控制块的任务调度器结合使用。 当PIO指令引用本地I / O总线上的器件时，输入/输出过程正常执行。 要在远程处理器上执行输入/输出过程，将标识远程处理器的锁定描述符放置在该进程的过程控制块中。 然后输入/输出过程被安排在远程处理器上执行。

公开(公告)号：EP0192419A3

公开(公告)日：1987-12-09

申请号：EP86300987

申请日：1986-02-13

Applicant: PRIME COMPUTER, INC.

Inventor： Irukulla, Suren ,  Patel, Bimal V.

IPC: G06F07/52 ,  G06F01/02

CPC classification number: G06F7/535 ,  G06F1/0356 ,  G06F2207/5354

Abstract: The invention relates to a range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2 -n . The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.

公开(公告)号：EP0153106A3

公开(公告)日：1987-05-27

申请号：EP85300855

申请日：1985-02-08

Applicant: PRIME COMPUTER, INC.

Inventor： TURNER, PRESCOTT K.

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/447

Abstract: A compiler for generating an assembly language listing of instructions for a programmable data processor from a high level programming language has elements for generating from the high level programming language input, an intermediate representation of the programming language input and for generating from the intermediate representation, an assembly language representation of the high level programming lan­ guage input. The compiler operates generally in accordance with the Glanville-Graham method which enables the compiler to be used with different machines. The resulting retargetable compiler is improved by employing an up/down parsing meth­ od in the code generator portion which removes significant re­ strictions found when LR parsing is employed. The parsing method allows preprocessing of the prefix grammer represent­ ing the input intermediate representation for producing, for use by the code generator parsing element, a state table, an ex­ tended state table, and a state transition table.

公开(公告)号：EP0192420A2

公开(公告)日：1986-08-27

申请号：EP86300988.2

申请日：1986-02-13

Applicant: PRIME COMPUTER, INC.

Inventor： Irukulla, Suren ,  Patel, Bimal V

IPC: G06F7/52 ,  G06F7/49

CPC classification number: G06F7/535 ,  G06F7/49 ,  G06F7/4917 ,  G06F7/5375

Abstract: The invention provides a method and apparatus for radix-p non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-p quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-p digit of each of these partial remainders, the process generates a radix-β quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating succesively generated quotient digits to produce a final quotient value.

Abstract translation: 本发明提供了一种用于基数β不恢复分割的方法和装置。 分割过程分四个阶段进行。 在第一阶段中，输入操作数被变换以产生位于指定数值范围内的除数。 接下来，过渡阶段涉及从转换的分子生成初始的基数β商数。 该过程的迭代阶段根据递归方法产生连续的部分余数。 从符号和每个这些部分余数的单个基数β数字，该过程生成基数β商数。 此外，可以与过渡和迭代阶段同时运行的第四阶段涉及累积随后生成的商数，以产生最终商值。

公开(公告)号：EP0192419A2

公开(公告)日：1986-08-27

申请号：EP86300987.4

申请日：1986-02-13

Applicant: PRIME COMPUTER, INC.

Inventor： Irukulla, Suren ,  Patel, Bimal V.

IPC: G06F7/52 ,  G06F1/02

CPC classification number: G06F7/535 ,  G06F1/0356 ,  G06F2207/5354

Abstract: The invention relates to a range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2 -n . The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.

Abstract translation: 本发明涉及的范围内变换方法，用于通过不超过数量2 转化的归一化除数的除法计算的一系列worin的转化的值从一个不同。 该方法和装置产生的从第1高顺序从至少那些相同位数变换乘数值除数的“Q”的数字和产生外的范围指示信号。 当外的范围内的条件被表示这样生成的乘数的值响应于外的范围指示信号修改。 该装置采用一个只读存储器，用于使变换乘法器值的生成，而不需要或大查表存储或乘法函数。 其结果是，各个分割方法在初始转换需要提供一种在除数一个值，其方法可以高效地实现。

公开(公告)号：EP0119445A3

公开(公告)日：1985-12-04

申请号：EP84101376

申请日：1984-02-10

Applicant: PRIME COMPUTER, INC.

Inventor： Long, Charles Comey ,  Lounsbury, David Morgan ,  Curtin, Richard Roy

IPC: G11B05/09 ,  H04L25/49

CPC classification number: G11B20/1419

Abstract: Apparatus is disclosed for reading phase encoded digital data from a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accomodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns. Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing "window" during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established. The circuitry accomodates clock signal phase changes caused by bit shifting by calculating an expected arrival time for a data transition and varying the width of the timing window depending on whether the data transition is received either prior to or subsequent to the expected arrival time.

公开(公告)号：EP0153109A2

公开(公告)日：1985-08-28

申请号：EP85300859.7

申请日：1985-02-08

Applicant: PRIME COMPUTER, INC.

Inventor： Rodman, Paul K.

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0817

Abstract: A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjunction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents. Each element of the list defines one of those cache storage locations and also identifies the location in the CIT memory of the next element in the list.

Abstract translation: 一种用于多处理器系统的高速缓存一致性系统，包括耦合到公共主存储器的多个数据处理器。 每个数据处理器包括相关联的高速缓存存储器，其中存储位置对应于主存储器中的存储位置。 用于数据处理器的高速缓存一致性系统包括具有对应于数据处理器的高速缓冲存储器中的位置的内部存储位置的高速缓存无效表（CIT）存储器。 高速缓存一致性系统检测一个或多个数据处理器的高速缓冲存储器中的存储位置的内容何时已经与这些数据处理器的活动一起被修改并且响应于这种检测来生成和存储在其CIT存储器中 多元素链接列表定义具有修改内容的数据处理器的高速缓冲存储器中的位置。 列表的每个元素定义了这些缓存存储位置之一，并且还标识了列表中下一个元素的CIT存储器中的位置。