公开(公告)号：US12061888B2

公开(公告)日：2024-08-13

申请号：US17882292

申请日：2022-08-05

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Michel Jaouen ,  Gilles Trottier

IPC: G06F8/60 ,  G06F9/445 ,  G06F21/52

CPC classification number: G06F8/60 ,  G06F9/445 ,  G06F21/52

Abstract: A method can be used for verifying an execution of a compiled software program stored in a program memory of a processor and executed by the processor. A write operation includes assigning a destination address in a register of the processor and writing a datum at a location pointed to by the destination address contained in the register. A verification operation includes reassigning the same destination address in the same register, reading the datum contained at the location pointed to by the destination address contained in the register after the reassignment, and comparing the read datum and the written datum.

公开(公告)号：US20240211611A1

公开(公告)日：2024-06-27

申请号：US18543323

申请日：2023-12-18

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Michel JAOUEN

IPC: G06F21/60 ,  G06F21/57 ,  G06F21/78

CPC classification number: G06F21/602 ,  G06F21/57 ,  G06F21/78

Abstract: An electronic device is configured to support at least two configurations, one of the configurations being installed. The device includes a memory. In a limited-access region of the memory, a binary word is stored. That binary word has: a first value representative of the version of the installed configuration; and at least one second value indicating which configurations can be installed. A method of configuration of the electronic device includes determining, according to the second value, whether the configuration which attempts to be installed is permitted.

公开(公告)号：US11829188B2

公开(公告)日：2023-11-28

申请号：US16953993

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy ,  Nicolas Anquet ,  Dragos Davidescu

IPC: G06F11/00 ,  G06F11/07 ,  G06F13/42 ,  G06F21/44 ,  G06F11/36

CPC classification number: G06F11/0751 ,  G06F11/0721 ,  G06F11/3656 ,  G06F13/4282 ,  G06F21/44 ,  G06F2213/0016 ,  G06F2213/0038

Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

公开(公告)号：US20230170922A1

公开(公告)日：2023-06-01

申请号：US17962961

申请日：2022-10-10

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Francois Sittler

IPC: H04B1/00

CPC classification number: H04B1/0067 ,  H04B1/0064

Abstract: The present description concerns a communication device including a first communication circuit coupled to a first antenna port of the communication device; a switch having first, second and third terminals, the first terminal being coupled to a second antenna port of the communication device, the switch being configured to switch between a first state in which the first terminal is coupled t the second terminal and a second state in which the first terminal is coupled to the third terminal; a third port coupled to the second terminal of the switch; and a second communication circuit coupled to the third terminal.

公开(公告)号：US20230161486A1

公开(公告)日：2023-05-25

申请号：US18058613

申请日：2022-11-23

Applicant: STMicroelectronics (Grand Ouest)SAS

Inventor： Loic Pallardy ,  Michel Jaouen

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: In accordance with an embodiment, a method for managing a memory within a system-on-a-chip including a processor, a memory and a firewall device, includes: generating, by the processor, a request to access the memory, where the request has a access permission level; controlling, by the firewall device, access to the at least one memory region of the memory as a function of the access permission level of the request and a respective access permission level associated with at least one memory region; and erasing, by the firewall device, the at least one memory regions when its respective access permission level is modified, where erasing comprises performing a hardware-implemented erasure.

公开(公告)号：US20230161484A1

公开(公告)日：2023-05-25

申请号：US17989389

申请日：2022-11-17

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy ,  Michel Jaouen

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0673

Abstract: In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.

公开(公告)号：US11658576B2

公开(公告)日：2023-05-23

申请号：US17648471

申请日：2022-01-20

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Lionel Cimaz

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M1/082 ,  H02M1/0012 ,  H02M1/0022

Abstract: An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.

公开(公告)号：US20230153102A1

公开(公告)日：2023-05-18

申请号：US18156550

申请日：2023-01-19

Applicant: Proton World International N.V. ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Fabien Arrivé ,  Olivier Leo E. Collart

IPC: G06F8/65 ,  G06F21/64

CPC classification number: G06F8/65 ,  G06F21/64

Abstract: A device includes a memory, a first firmware copy of the device stored in a first position of the memory and a second firmware copy of the device stored in a second position of the memory, where each of the first firmware copy and the second firmware copy includes instructions, when executed by the device, perform an operation of the device; and a first delta copy associated with the first firmware copy. The first delta copy includes instructions that differ from the first firmware copy when executed at the first position and are the same when executed at the second position. The device is configured to receive the first delta copy from an external system and store the first delta copy in the memory.

公开(公告)号：US20230022755A1

公开(公告)日：2023-01-26

申请号：US17868456

申请日：2022-07-19

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Fabien GREGOIRE

IPC: G06F8/61 ,  G06F21/44

Abstract: A system on chip includes a non-volatile memory and a processor configured to execute an operating system which receives data according to a first communication protocol and program installation software that communicates with the non-volatile memory according to a second communication protocol. The operating system functions to: determine whether data received according to the first communication protocol is program data, make the program data available to the installation software, and inform the installation software that program data has been received. The installation software then stores the program data in the non-volatile memory.

公开(公告)号：US20220342655A1

公开(公告)日：2022-10-27

申请号：US17660092

申请日：2022-04-21

Applicant: STMicroelectronics (Grand Ouest) SAS

Inventor： Frederic RUELLE

IPC: G06F8/65 ,  G06F8/41 ,  G06F12/14

Abstract: According to one aspect, a method adds an additional function to a computer program installed on a microcontroller, the computer program using a table configured to associate an identifier of the additional function with a pointer to a memory address. The method includes the microcontroller obtaining a compiled code of the additional function and an identifier of this additional function, the microcontroller recording the compiled code of the additional function in a section of a memory, and recording in memory a pointer in the table, the pointer being aimed at the address of the memory section in which the compiled code of the additional function is recorded, the pointer being associated in the table with the identifier of the additional function.