公开(公告)号：FR3029687A1

公开(公告)日：2016-06-10

申请号：FR1462110

申请日：2014-12-09

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： SORRIEUL MARIKA ,  SAXOD KARINE

IPC: H01L21/82 ,  H01L21/56 ,  H01L27/14 ,  H01L31/0203

Abstract: Procédé de fabrication de dispositifs électroniques et dispositif électronique, dans lesquels une puce de circuits intégrés (3) est montée au-dessus d'une plaquette de support (2), une plaquette de protection (12) est montée au-dessus de la puce, un bloc d'encapsulation (18) est aménagé autour de la puce et de la plaquette de protection et sur une partie périphérique de la face avant de la plaquette de support. Le bloc d'encapsulation comprenant : un premier anneau d'encapsulation (19) aménagé autour de la puce et de la plaque de protection, présentant un bourrelet annulaire (20) en saillie par rapport à la face avant de la plaquette de protection et formant une rainure périphérique (24) en retrait par rapport à ce bourrelet annulaire en saillie, et un second anneau d'encapsulation (25) qui remplit la rainure périphérique (24) du premier anneau d'encapsulation.

公开(公告)号：FR3029292A1

公开(公告)日：2016-06-03

申请号：FR1461773

申请日：2014-12-02

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： MASSON THIERRY ,  PONTAROLLO SERGE

IPC: G01R17/06 ,  G01R17/10

Abstract: Le dispositif électronique, comprend un circuit de pont de Wheatstone (PW) et un circuit de correction (CC) couplé au circuit de pont de Wheatstone (PW) et configuré pour corriger un décalage de la tension de sortie de pont de Wheatstone (PW). Le circuit de correction (CC) comprend une interface d'entrée (7) pour recevoir une première tension, un module d'alimentation (1) configuré pour alimenter le circuit de pont de Wheatstone (PW) avec une deuxième tension tirée de la première tension et un premier courant (I1) asservi sur la valeur courante des résistances du circuit de pont de Wheatstone (PW) et élaborer un deuxième courant (12) proportionnel au premier courant (I1), et un convertisseur numérique-analogique (CNA) en courant configuré pour délivrer un courant de correction aux sorties (2, 3) du circuit de pont de Wheatstone (PW) à partir d'un signal numérique de correction (SNC) et du deuxième courant (12).

公开(公告)号：DE102015115230A1

公开(公告)日：2016-06-02

申请号：DE102015115230

申请日：2015-09-10

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： MASSON THIERRY ,  PONTAROLLO SERGE

IPC: G01R17/06 ,  G01R17/10 ,  G01R35/00

Abstract: Die elektronische Vorrichtung weist eine Wheatstone-Brückenschaltung (PW) und eine Korrekturschaltung (CC) auf, die mit der Wheatstone-Brückenschaltung (PW) gekoppelt ist und die zur Korrektur einer Verschiebung der Ausgangsspannung der Wheatstone-Brücke ausgestaltet ist. Die Korrekturschaltung (CC) weist eine Eingangsschnittstelle (7) auf zum Empfangen einer ersten Spannung, ein Versorgungsmodul (1), das ausgestaltet ist, um die Wheatstone-Brückenschaltung (PW) mit einer zweiten Spannung, die aus der ersten Spannung entnommen wird, zu versorgen, und einen ersten Strom (I1), der aufgrund des aktuellen Wertes der Widerstände der Wheatstone-Brückenschaltung (PW) geregelt wird, sowie um einen zweiten Strom (I2), der proportional zum ersten Strom (I1) ist, zu erzeugen, sowie einen Digital-Analog-Stromwandler (CNA), der ausgestaltet ist, um einen Korrekturstrom an den Ausgängen (2, 3) der Wheatstone-Brückenschaltung (PW) anhand eines digitalen Korrektursignals (SNC) und des zweiten Stroms (I2) zu liefern.

公开(公告)号：US12272922B2

公开(公告)日：2025-04-08

申请号：US18408149

申请日：2024-01-09

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Fabien Quercia ,  Jean-Michel Riviere

IPC: H01S5/02345 ,  H01L23/00

Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.

公开(公告)号：US12266613B2

公开(公告)日：2025-04-01

申请号：US17847330

申请日：2022-06-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Claire Laporte ,  Laurent Schwartz ,  Godfrey Dimayuga

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

Abstract: A support substrate has a mounting face and a connection face opposite to the mounting face. An electronic chip is mounted to the mounting face and a matrix of connectors is mounted to the connection face. The support substrate includes an interconnection structure formed by a pair of conductive interconnection tracks that electrically connect the electronic chip to the matrix of connectors and circulate differential signals. The two interconnection tracks of the pair of conductive interconnection tracks extend facing each other at different depths of the support substrate. An isolation structure in the support substrate laterally isolates the pair of conductive interconnection tracks. Isolation plates above and below the pair of conductive interconnection tracks provide further isolation.

公开(公告)号：US12249549B2

公开(公告)日：2025-03-11

申请号：US18630676

申请日：2024-04-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Lopez

IPC: H01L23/31 ,  H01L23/10 ,  H01L23/12 ,  H01L33/52

Abstract: An encapsulation hood is fastened onto electrically conductive zones of a support substrate using springs. Each spring has a region in contact with an electrically conductive path contained in the encapsulation hood and another region in contact with a corresponding one of the electrically conductive zones. The fastening of the part of the encapsulation hood onto the support substrate compresses the springs and further utilizes a bead of insulating glue located between the compressed springs.

公开(公告)号：US20250070081A1

公开(公告)日：2025-02-27

申请号：US18947819

申请日：2024-11-14

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20250004051A1

公开(公告)日：2025-01-02

申请号：US18883619

申请日：2024-09-12

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Mark Trimmer

IPC: G01R31/317 ,  G01R31/3185 ,  G06F12/14 ,  G11C29/10

Abstract: The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

公开(公告)号：US20240402778A1

公开(公告)日：2024-12-05

申请号：US18798023

申请日：2024-08-08

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Christophe Lorin ,  Nathalie Ballot

IPC: G06F1/26 ,  G06F13/40

Abstract: The present disclosure relates to an USB PD-type interface including a first node receiving a first potential, a second node delivering a second potential, and a third node at a reference potential; a resistor connected between a fourth node coupled to the first node, and a fifth node; a MOS transistor connected between the fifth node and the second node; a bipolar transistor having a collector connected to a gate of the MOS transistor and an emitter connected to the fourth node or the fifth node; and a circuit configured to deliver a control potential to a base of the bipolar transistor determined from a current in the first resistor.

公开(公告)号：US12158483B2

公开(公告)日：2024-12-03

申请号：US18053974

申请日：2022-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Christophe Lorin

IPC: G01R15/14 ,  G01R1/20 ,  G01R27/14

Abstract: In accordance with an embodiment, an integrated circuit chip includes a first input configured to receive a rectified potential and a second input configured to receive a reference potential; a first circuit configured to maintain the rectified potential at a constant value on the first input; a second circuit having a power supply input coupled to the first node; a first resistor series-connected to the first circuit between the second input and the first node, or connected between the first input and the first node; a third circuit connected across the first resistor and configured to deliver a signal which is an image of a current in the first resistor; and a fourth circuit configured to determine a mains frequency and/or a mains voltage based at least on the signal which is the image of the current in the first resistor.